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fix more dead links
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lizzie
@@ -40,7 +40,7 @@ Dedicated shader recompiler to translate Maxwell assembly code to either SPIR-V,
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## src/video_core/
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Most of the things here have their own dedicated section. In short this is basically the entire Tegra NVIDIA Maxwell GPU emulation. Additionally it includes some [extra effects](../src/video_core/host_ahders) to emulate MSAA, D24 copies or as polyfill.
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Most of the things here have their own dedicated section. In short this is basically the entire Tegra NVIDIA Maxwell GPU emulation. Additionally it includes some [extra effects](../src/video_core/host_shaders/opengl_smaa.glsl) to emulate MSAA, D24 copies or as polyfill.
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Available backends are: Null, Vulkan, and OpenGL.
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+13
-13
@@ -5,14 +5,14 @@ support for other versions of the ARM architecture, having a interpreter mode, a
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for other architectures.
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Users of this library interact with it primarily through the interface provided in
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[`src/dynarmic/interface`](../src/dynarmic/interface). Users specify how Dynarmic's CPU core interacts with
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[`src/dynarmic/interface`](../../src/dynarmic/interface). Users specify how Dynarmic's CPU core interacts with
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the rest of their system providing an implementation of the relevant `UserCallbacks` interface.
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Users setup the CPU state using member functions of `Jit`, then call `Jit::Execute` to start CPU
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execution. The callbacks defined on `UserCallbacks` may be called from dynamically generated code,
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so users of the library should not depend on the stack being in a walkable state for unwinding.
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* A32: [`Jit`](../src/dynarmic/interface/A32/a32.h), [`UserCallbacks`](../src/dynarmic/interface/A32/config.h)
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* A64: [`Jit`](../src/dynarmic/interface/A64/a64.h), [`UserCallbacks`](../src/dynarmic/interface/A64/config.h)
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* A32: [`Jit`](../../src/dynarmic/interface/A32/a32.h), [`UserCallbacks`](../../src/dynarmic/interface/A32/config.h)
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* A64: [`Jit`](../../src/dynarmic/interface/A64/a64.h), [`UserCallbacks`](../../src/dynarmic/interface/A64/config.h)
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Dynarmic reads instructions from memory by calling `UserCallbacks::MemoryReadCode`. These
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instructions then pass through several stages:
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@@ -26,19 +26,19 @@ instructions then pass through several stages:
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Using the A32 frontend with the x64 backend as an example:
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* Decoding is done by [double dispatch](https://en.wikipedia.org/wiki/Visitor_pattern) in
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../src/dynarmic/frontend/A32/decoder/).
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* Translation is done by the visitors in [`src/dynarmic/frontend/A32/translate/translate_{arm,thumb}.cpp`](../src/dynarmic/frontend/A32/translate/).
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The function [`Translate`](../src/dynarmic/frontend/A32/translate/translate.h) takes a starting memory location,
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../../src/dynarmic/frontend/A32/decoder/).
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* Translation is done by the visitors in [`src/dynarmic/frontend/A32/translate/translate_{arm,thumb}.cpp`](../../src/dynarmic/frontend/A32/translate/).
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The function [`Translate`](../../src/dynarmic/frontend/A32/translate/translate.h) takes a starting memory location,
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some CPU state, and memory reader callback and returns a basic block of IR.
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* The IR can be found under [`src/frontend/ir/`](../src/dynarmic/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/dynarmic/ir/opt/).
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* Emission is done by `EmitX64` which can be found in [`src/dynarmic/backend/x64/emit_x64.{h,cpp}`](../src/dynarmic/backend/x64/).
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* Execution is performed by calling `BlockOfCode::RunCode` in [`src/dynarmic/backend/x64/block_of_code.{h,cpp}`](../src/dynarmic/backend/x64/).
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* The IR can be found under [`src/frontend/ir/`](../../src/dynarmic/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../../src/dynarmic/ir/opt/).
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* Emission is done by `EmitX64` which can be found in [`src/dynarmic/backend/x64/emit_x64.{h,cpp}`](../../src/dynarmic/backend/x64/).
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* Execution is performed by calling `BlockOfCode::RunCode` in [`src/dynarmic/backend/x64/block_of_code.{h,cpp}`](../../src/dynarmic/backend/x64/).
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## Decoder
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The decoder is a double dispatch decoder. Each instruction is represented by a line in the relevant
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instruction table. Here is an example line from [`arm.h`](../src/dynarmic/frontend/A32/decoder/arm.h):
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instruction table. Here is an example line from [`arm.h`](../../src/dynarmic/frontend/A32/decoder/arm.h):
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv")
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@@ -61,7 +61,7 @@ error results.
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## Translator
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The translator is a visitor that uses the decoder to decode instructions. The translator generates IR code with the
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help of the [`IREmitter` class](../src/dynarmic/ir/ir_emitter.h). An example of a translation function follows:
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help of the [`IREmitter` class](../../src/dynarmic/ir/ir_emitter.h). An example of a translation function follows:
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bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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@@ -107,7 +107,7 @@ function analyser in the medium-term future.
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Dynarmic's intermediate representation is typed. Each microinstruction may take zero or more arguments and may
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return zero or more arguments. A subset of the microinstructions available is documented below.
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A complete list of microinstructions can be found in [src/dynarmic/ir/opcodes.inc](../src/dynarmic/ir/opcodes.inc).
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A complete list of microinstructions can be found in [src/dynarmic/ir/opcodes.inc](../../src/dynarmic/ir/opcodes.inc).
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The below lists some commonly used microinstructions.
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@@ -5,7 +5,7 @@ A dynamic recompiler for ARM.
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*Note that an adversarial guest program [can determine if it's being ran under Dynarmic](#disadvantages-of-dynarmic). Preventing this is not a goal of this project.*
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Cortex-A57 (32 and 64 bit) is the emulated guest target. See [ArchVersion](src/dynarmic/interface/A32/arch_version.h).
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Cortex-A57 (32 and 64 bit) is the emulated guest target. See [ArchVersion](../../src/dynarmic/interface/A32/arch_version.h).
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The only supported host architectures are x86-64, and AArch64. There are no plans to support any 32-bit architectures.
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@@ -81,7 +81,7 @@ Tacit support for down to XP is provided for interested hobbyists. Read below.
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DirectX 12 is not available - simply copy and paste any DLL and name it `d3d12.dll`.
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Install [Qt6 compatibility libraries](github.com/ANightly/qt6windows7) specifically Qt 6.9.5.
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Install [Qt6 compatibility libraries](https://github.com/ANightly/qt6windows7) specifically Qt 6.9.5.
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### Windows XP, Vista
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@@ -47,7 +47,7 @@ Use this guide when you want to set up specific controller profiles for specific
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- Eden Emulator set up and fully configured
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- Controller Profile Created
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- See [*Configuring Controller Profiles*](./ControllerProfiles.md) for instructions on how to do this if needed.
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- See [*Configuring Controller Profiles*](./Controllers.md#configuring-controller-profiles) for instructions on how to do this if needed.
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---
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@@ -49,6 +49,4 @@ A copy of this handbook is [available online](https://git.eden-emu.dev/eden-emu/
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- **[Gyro Controls](./GyroControls.md)**
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- **[Platforms and Architectures](./Architectures.md)**
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- **[Native Application Development](./Native.md)**
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- **[Adding Boolean Settings Toggles](./AddingBooleanToggles.md)**
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- **[Adding Debug Knobs](./AddingDebugKnobs.md)**
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- **[Testing](./Testing.md)**
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@@ -96,4 +96,4 @@ The faulty commit then, is 6th of Jan. This is called bisection https://git-scm.
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- PR's marked with **WIP** do NOT need to be tested unless explicitly asked (check the git in case)
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- Sometimes license checks may fail, hover over the build icon to see if builds did succeed, as the CI will push builds even if license checks fail.
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- All open PRs can be viewed [here](https://git.eden-emu.dev/eden-emu/eden/pulls/).
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- If site is down use one of the [mirrors](./user/ThirdParty.md#mirrors).
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- If site is down use one of the [mirrors](./ThirdParty.md#mirrors).
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