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Revert "[vk] Fix Vulkan Upload & Present Barriers for Spec Compliance (#2681)" (#2748)

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Vulkan layout and barrier edits made the GPU use a different shader path that compiled a TLDS instruction with an unaligned register (R157).

The old path never generated that case, so the translator’s missing unaligned-register handling only surfaced after this change.

Co-authored-by: Ribbit <ribbit@placeholder.com>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2748
Reviewed-by: MaranBr <maranbr@eden-emu.dev>
Co-authored-by: Ribbit <ribbit@eden-emu.dev>
Co-committed-by: Ribbit <ribbit@eden-emu.dev>
This commit is contained in:
Ribbit
2025-10-16 03:33:24 +02:00
committed by crueter
parent 31463142e1
commit 30482692c7
3 changed files with 4 additions and 4 deletions
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src/video_core/renderer_vulkan/present/layer.cpp
+1 -1
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@@ -332,7 +332,7 @@ void Layer::UpdateRawImage(const Tegra::FramebufferConfig& framebuffer, size_t i
write_barrier.dstAccessMask = VK_ACCESS_SHADER_READ_BIT;
write_barrier.oldLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT, 0,
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_HOST_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT, 0,
read_barrier);
cmdbuf.CopyBufferToImage(*buffer, image, VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL, copy);
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT,