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[video_core, hle] remove redundant parent references in system structs (#3908)

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reworked a bit to remove references of parent objects and instead pass as arguments to methods to prevent useless reloads

Signed-off-by: lizzie <lizzie@eden-emu.dev>
Co-authored-by: maufeat <sahyno1996@gmail.com>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3908
Reviewed-by: Maufeat <sahyno1996@gmail.com>
Reviewed-by: crueter <crueter@eden-emu.dev>
This commit is contained in:
lizzie
2026-06-23 06:31:25 +02:00
committed by crueter
parent f8facda35f
commit 3aa0d46259
307 changed files with 4419 additions and 4477 deletions
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src/video_core/gpu.cpp
+58 -124
View File
@@ -40,30 +40,31 @@
namespace Tegra {
struct GPU::Impl {
explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
: gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_},
shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {}
explicit Impl(Core::System& system_, bool is_async_, bool use_nvdec_)
: system{system_}
, use_nvdec{use_nvdec_}
, shader_notify()
, is_async{is_async_}
, gpu_thread{system_}
{}
~Impl() = default;
std::shared_ptr<Control::ChannelState> CreateChannel(s32 channel_id) {
auto channel_state = std::make_shared<Tegra::Control::ChannelState>(channel_id);
channels.emplace(channel_id, channel_state);
scheduler->DeclareChannel(channel_state);
scheduler.DeclareChannel(channel_state);
return channel_state;
}
void BindChannel(s32 channel_id) {
if (bound_channel == channel_id) {
return;
if (bound_channel != channel_id) {
auto it = channels.find(channel_id);
ASSERT(it != channels.end());
bound_channel = channel_id;
current_channel = it->second.get();
renderer->ReadRasterizer()->BindChannel(*current_channel);
}
auto it = channels.find(channel_id);
ASSERT(it != channels.end());
bound_channel = channel_id;
current_channel = it->second.get();
rasterizer->BindChannel(*current_channel);
}
std::shared_ptr<Control::ChannelState> AllocateChannel() {
@@ -71,13 +72,13 @@ struct GPU::Impl {
}
void InitChannel(Control::ChannelState& to_init, u64 program_id) {
to_init.Init(system, gpu, program_id);
to_init.BindRasterizer(rasterizer);
rasterizer->InitializeChannel(to_init);
to_init.Init(system, program_id);
to_init.BindRasterizer(renderer->ReadRasterizer());
renderer->ReadRasterizer()->InitializeChannel(to_init);
}
void InitAddressSpace(Tegra::MemoryManager& memory_manager) {
memory_manager.BindRasterizer(rasterizer);
memory_manager.BindRasterizer(renderer->ReadRasterizer());
}
void ReleaseChannel(Control::ChannelState& to_release) {
@@ -87,26 +88,26 @@ struct GPU::Impl {
/// Binds a renderer to the GPU.
void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
renderer = std::move(renderer_);
rasterizer = renderer->ReadRasterizer();
host1x.MemoryManager().BindInterface(rasterizer);
host1x.gmmu_manager.BindRasterizer(rasterizer);
system.Host1x().memory_manager.BindInterface(renderer->ReadRasterizer());
system.Host1x().gmmu_manager.BindRasterizer(renderer->ReadRasterizer());
}
/// Flush all current written commands into the host GPU for execution.
void FlushCommands() {
rasterizer->FlushCommands();
renderer->ReadRasterizer()->FlushCommands();
}
/// Synchronizes CPU writes with Host GPU memory.
void InvalidateGPUCache() {
std::function<void(PAddr, size_t)> callback_writes(
[this](PAddr address, size_t size) { rasterizer->OnCacheInvalidation(address, size); });
std::function<void(PAddr, size_t)> callback_writes([this](PAddr address, size_t size) {
renderer->ReadRasterizer()->OnCacheInvalidation(address, size);
});
system.GatherGPUDirtyMemory(callback_writes);
}
/// Signal the ending of command list.
void OnCommandListEnd() {
rasterizer->ReleaseFences(false);
renderer->ReadRasterizer()->ReleaseFences(false);
Settings::UpdateGPUAccuracy();
}
@@ -143,62 +144,6 @@ struct GPU::Impl {
}
}
/// Returns a reference to the Maxwell3D GPU engine.
[[nodiscard]] Engines::Maxwell3D& Maxwell3D() {
ASSERT(current_channel);
return *current_channel->maxwell_3d;
}
/// Returns a const reference to the Maxwell3D GPU engine.
[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const {
ASSERT(current_channel);
return *current_channel->maxwell_3d;
}
/// Returns a reference to the KeplerCompute GPU engine.
[[nodiscard]] Engines::KeplerCompute& KeplerCompute() {
ASSERT(current_channel);
return *current_channel->kepler_compute;
}
/// Returns a reference to the KeplerCompute GPU engine.
[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const {
ASSERT(current_channel);
return *current_channel->kepler_compute;
}
/// Returns a reference to the GPU DMA pusher.
[[nodiscard]] Tegra::DmaPusher& DmaPusher() {
ASSERT(current_channel);
return *current_channel->dma_pusher;
}
/// Returns a const reference to the GPU DMA pusher.
[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const {
ASSERT(current_channel);
return *current_channel->dma_pusher;
}
/// Returns a reference to the underlying renderer.
[[nodiscard]] VideoCore::RendererBase& Renderer() {
return *renderer;
}
/// Returns a const reference to the underlying renderer.
[[nodiscard]] const VideoCore::RendererBase& Renderer() const {
return *renderer;
}
/// Returns a reference to the shader notifier.
[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() {
return *shader_notify;
}
/// Returns a const reference to the shader notifier.
[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const {
return *shader_notify;
}
[[nodiscard]] u64 GetTicks() const {
u64 gpu_tick = system.CoreTiming().GetGPUTicks();
Settings::GpuOverclock overclock = Settings::values.fast_gpu_time.GetValue();
@@ -210,14 +155,6 @@ struct GPU::Impl {
return gpu_tick;
}
[[nodiscard]] bool IsAsync() const {
return is_async;
}
[[nodiscard]] bool UseNvdec() const {
return use_nvdec;
}
void RendererFrameEndNotify() {
system.GetPerfStats().EndGameFrame();
}
@@ -227,7 +164,7 @@ struct GPU::Impl {
/// core timing events.
void Start() {
Settings::UpdateGPUAccuracy();
gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler);
gpu_thread.StartThread(*renderer, renderer->Context(), scheduler);
}
void NotifyShutdown() {
@@ -251,25 +188,24 @@ struct GPU::Impl {
/// Push GPU command entries to be processed
void PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
gpu_thread.SubmitList(channel, std::move(entries));
gpu_thread.SubmitList(channel, std::move(entries), is_async);
}
/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
void FlushRegion(DAddr addr, u64 size) {
gpu_thread.FlushRegion(addr, size);
gpu_thread.FlushRegion(addr, size, is_async);
}
VideoCore::RasterizerDownloadArea OnCPURead(DAddr addr, u64 size) {
auto raster_area = rasterizer->GetFlushArea(addr, size);
auto raster_area = renderer->ReadRasterizer()->GetFlushArea(addr, size);
if (raster_area.preemtive) {
return raster_area;
}
raster_area.preemtive = true;
const u64 fence = RequestSyncOperation([this, &raster_area]() {
rasterizer->FlushRegion(raster_area.start_address,
raster_area.end_address - raster_area.start_address);
renderer->ReadRasterizer()->FlushRegion(raster_area.start_address, raster_area.end_address - raster_area.start_address);
});
gpu_thread.TickGPU();
gpu_thread.TickGPU(is_async);
WaitForSyncOperation(fence);
return raster_area;
}
@@ -280,16 +216,15 @@ struct GPU::Impl {
}
bool OnCPUWrite(DAddr addr, u64 size) {
return rasterizer->OnCPUWrite(addr, size);
return renderer->ReadRasterizer()->OnCPUWrite(addr, size);
}
/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
void FlushAndInvalidateRegion(DAddr addr, u64 size) {
gpu_thread.FlushAndInvalidateRegion(addr, size);
gpu_thread.FlushAndInvalidateRegion(addr, size, is_async);
}
void RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
std::vector<Service::Nvidia::NvFence>&& fences) {
void RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers, std::vector<Service::Nvidia::NvFence>&& fences) {
size_t num_fences{fences.size()};
size_t current_request_counter{};
{
@@ -304,7 +239,7 @@ struct GPU::Impl {
}
}
const auto wait_fence = RequestSyncOperation([this, current_request_counter, &layers, &fences, num_fences] {
auto& syncpoint_manager = host1x.GetSyncpointManager();
auto& syncpoint_manager = system.Host1x().GetSyncpointManager();
if (num_fences == 0) {
renderer->Composite(layers);
}
@@ -322,7 +257,7 @@ struct GPU::Impl {
syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer);
}
});
gpu_thread.TickGPU();
gpu_thread.TickGPU(is_async);
WaitForSyncOperation(wait_fence);
}
@@ -331,23 +266,20 @@ struct GPU::Impl {
const auto wait_fence =
RequestSyncOperation([&] { out = renderer->GetAppletCaptureBuffer(); });
gpu_thread.TickGPU();
gpu_thread.TickGPU(is_async);
WaitForSyncOperation(wait_fence);
return out;
}
GPU& gpu;
Core::System& system;
Host1x::Host1x& host1x;
std::unique_ptr<VideoCore::RendererBase> renderer;
VideoCore::RasterizerInterface* rasterizer = nullptr;
const bool use_nvdec;
s32 new_channel_id{1};
/// Shader build notifier
std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
VideoCore::ShaderNotify shader_notify;
/// When true, we are about to shut down emulation session, so terminate outstanding tasks
std::atomic_bool shutting_down{};
@@ -371,7 +303,7 @@ struct GPU::Impl {
VideoCommon::GPUThread::ThreadManager gpu_thread;
std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context;
std::unique_ptr<Tegra::Control::Scheduler> scheduler;
Tegra::Control::Scheduler scheduler;
ankerl::unordered_dense::map<s32, std::shared_ptr<Tegra::Control::ChannelState>> channels;
Tegra::Control::ChannelState* current_channel;
s32 bound_channel{-1};
@@ -382,7 +314,8 @@ struct GPU::Impl {
};
GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
: impl{std::make_unique<Impl>(system, is_async, use_nvdec)}
{}
GPU::~GPU() = default;
@@ -423,8 +356,9 @@ void GPU::OnCommandListEnd() {
}
u64 GPU::RequestFlush(DAddr addr, std::size_t size) {
return impl->RequestSyncOperation(
[this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); });
return impl->RequestSyncOperation([this, addr, size]() {
impl->renderer->ReadRasterizer()->FlushRegion(addr, size);
});
}
u64 GPU::CurrentSyncRequestFence() const {
@@ -441,52 +375,52 @@ void GPU::TickWork() {
/// Gets a mutable reference to the Host1x interface
Host1x::Host1x& GPU::Host1x() {
return impl->host1x;
return impl->system.Host1x();
}
/// Gets an immutable reference to the Host1x interface.
const Host1x::Host1x& GPU::Host1x() const {
return impl->host1x;
return impl->system.Host1x();
}
Engines::Maxwell3D& GPU::Maxwell3D() {
return impl->Maxwell3D();
return impl->current_channel->payload->maxwell_3d;
}
const Engines::Maxwell3D& GPU::Maxwell3D() const {
return impl->Maxwell3D();
return impl->current_channel->payload->maxwell_3d;
}
Engines::KeplerCompute& GPU::KeplerCompute() {
return impl->KeplerCompute();
return impl->current_channel->payload->kepler_compute;
}
const Engines::KeplerCompute& GPU::KeplerCompute() const {
return impl->KeplerCompute();
return impl->current_channel->payload->kepler_compute;
}
Tegra::DmaPusher& GPU::DmaPusher() {
return impl->DmaPusher();
return impl->current_channel->payload->dma_pusher;
}
const Tegra::DmaPusher& GPU::DmaPusher() const {
return impl->DmaPusher();
return impl->current_channel->payload->dma_pusher;
}
VideoCore::RendererBase& GPU::Renderer() {
return impl->Renderer();
return *impl->renderer;
}
const VideoCore::RendererBase& GPU::Renderer() const {
return impl->Renderer();
return *impl->renderer;
}
VideoCore::ShaderNotify& GPU::ShaderNotify() {
return impl->ShaderNotify();
return impl->shader_notify;
}
const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
return impl->ShaderNotify();
return impl->shader_notify;
}
void GPU::RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
@@ -503,11 +437,11 @@ u64 GPU::GetTicks() const {
}
bool GPU::IsAsync() const {
return impl->IsAsync();
return impl->is_async;
}
bool GPU::UseNvdec() const {
return impl->UseNvdec();
return impl->use_nvdec;
}
void GPU::RendererFrameEndNotify() {