[common/core/dynarmic] Optimize page table allocations (#4219)

Reduces the page entries from 32 bytes to 8 and rewrites `VirtualBuffer` to be more efficient in memory usage and specifically for large zero regions.

The page table will now only reserve 1GiB instead of 4GiB and of this memory it should only use at most ~8MiB.

This PR has the side effect of using Eden on Windows on low memory systems much more plausible since it would previously require ~10GiB of committable memory at front (despite using ~5-6 at most, inadvertently stalling other processes) where as now it should only require around the amount that it'll actually use.

Co-authored-by: Lizzie <lizzie@eden-emu.dev>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/4219
Reviewed-by: Maufeat <sahyno1996@gmail.com>
Reviewed-by: lizzie <lizzie@eden-emu.dev>
Reviewed-by: CamilleLaVey <camillelavey99@gmail.com>

src/dynarmic/src/dynarmic/backend/arm64/a32_address_space.cpp

@@ -371,8 +371,10 @@ EmitConfig A32AddressSpace::GetEmitConfig() {
 
         .page_table_pointer = std::bit_cast<u64>(conf.page_table),
         .page_table_address_space_bits = 32,
-        .page_table_pointer_mask_bits = conf.page_table_pointer_mask_bits,
+        .page_table_pointer_mask = conf.page_table_pointer_mask,
         .page_table_log2_stride = conf.page_table_log2_stride,
+        .page_table_marked_bit = conf.page_table_marked_bit,
+        .page_table_sign_extension = conf.page_table_sign_extension,
         .silently_mirror_page_table = true,
         .absolute_offset_page_table = conf.absolute_offset_page_table,
         .detect_misaligned_access_via_page_table = conf.detect_misaligned_access_via_page_table,

src/dynarmic/src/dynarmic/backend/arm64/a64_address_space.cpp

@@ -545,8 +545,10 @@ EmitConfig A64AddressSpace::GetEmitConfig() {
 
         .page_table_pointer = std::bit_cast<u64>(conf.page_table),
         .page_table_address_space_bits = conf.page_table_address_space_bits,
-        .page_table_pointer_mask_bits = conf.page_table_pointer_mask_bits,
+        .page_table_pointer_mask = conf.page_table_pointer_mask,
         .page_table_log2_stride = conf.page_table_log2_stride,
+        .page_table_marked_bit = conf.page_table_marked_bit,
+        .page_table_sign_extension = conf.page_table_sign_extension,
         .silently_mirror_page_table = conf.silently_mirror_page_table,
         .absolute_offset_page_table = conf.absolute_offset_page_table,
         .detect_misaligned_access_via_page_table = conf.detect_misaligned_access_via_page_table,

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.h

@@ -128,8 +128,10 @@ struct EmitConfig {
     // Page table
     u64 page_table_pointer;
     std::size_t page_table_address_space_bits;
-    int page_table_pointer_mask_bits;
+    u64 page_table_pointer_mask;
     std::size_t page_table_log2_stride;
+    std::optional<std::uint8_t> page_table_marked_bit;
+    std::optional<std::uint8_t> page_table_sign_extension;
     bool silently_mirror_page_table;
     bool absolute_offset_page_table;
     u8 detect_misaligned_access_via_page_table;

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp

@@ -273,9 +273,18 @@ std::pair<oaknut::XReg, oaknut::XReg> InlinePageTableEmitVAddrLookup(oaknut::Cod
     // load x0 = *<(u8*)pagetable + index>
     code.LDR(Xscratch0, Xpagetable, Xscratch0);
 
-    if (ctx.conf.page_table_pointer_mask_bits != 0) {
-        const u64 mask = u64(~u64(0)) << ctx.conf.page_table_pointer_mask_bits;
-        code.AND(Xscratch0, Xscratch0, mask);
+    if (ctx.conf.page_table_marked_bit) {
+        // check for marked bit
+        code.TBNZ(Xscratch0, *ctx.conf.page_table_marked_bit, *fallback);
+    }
+
+    if (ctx.conf.page_table_pointer_mask != 0) {
+        code.AND(Xscratch0, Xscratch0, ctx.conf.page_table_pointer_mask);
+    }
+
+    // TODO: combine this with page_table_pointer_mask
+    if (ctx.conf.page_table_sign_extension) {
+        code.SBFM(Xscratch0, Xscratch0, 0, *ctx.conf.page_table_sign_extension);
     }
 
     code.CBZ(Xscratch0, *fallback);

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h

@@ -9,6 +9,7 @@
 #pragma once
 
 #include <bit>
+#include <utility>
 #include "dynarmic/backend/x64/xbyak.h"
 
 #include "dynarmic/backend/x64/a32_emit_x64.h"
@@ -78,27 +79,40 @@ Xbyak::RegExp EmitVAddrLookup(BlockOfCode& code, EmitContext& ctx, size_t bitsiz
 template<>
 [[maybe_unused]] Xbyak::RegExp EmitVAddrLookup<A32EmitContext>(BlockOfCode& code, A32EmitContext& ctx, size_t bitsize, Xbyak::Label& abort, Xbyak::Reg64 vaddr) {
     const Xbyak::Reg64 page = ctx.reg_alloc.ScratchGpr(code);
-    const Xbyak::Reg32 tmp = ctx.conf.absolute_offset_page_table ? page.cvt32() : ctx.reg_alloc.ScratchGpr(code).cvt32();
+    const Xbyak::Reg64 tmp = ctx.conf.absolute_offset_page_table && ctx.conf.page_table_pointer_mask == 0 ? page : ctx.reg_alloc.ScratchGpr(code);
 
-    EmitDetectMisalignedVAddr(code, ctx, bitsize, abort, vaddr, tmp.cvt64());
+    EmitDetectMisalignedVAddr(code, ctx, bitsize, abort, vaddr, tmp);
 
-    // TODO: This code assumes vaddr has been zext from 32-bits to 64-bits.
-
-    code.mov(tmp, vaddr.cvt32());
+    code.mov(tmp, vaddr);
     code.shr(tmp, int(page_table_const_bits));
     code.shl(tmp, int(ctx.conf.page_table_log2_stride));
     code.mov(page, qword[r14 + tmp.cvt64()]);
-    if (ctx.conf.page_table_pointer_mask_bits == 0) {
+
+    // check for marked bit, use as unmapped if marked
+	if (ctx.conf.page_table_marked_bit) {
+        code.bt(page, *ctx.conf.page_table_marked_bit);
+        code.jc(abort, code.T_NEAR);
+	}
+    // mask away attributes
+    if (ctx.conf.page_table_pointer_mask == 0) {
         code.test(page, page);
+    } else if (std::in_range<s32>(ctx.conf.page_table_pointer_mask)) {
+        code.and_(page, ctx.conf.page_table_pointer_mask);
     } else {
-        code.and_(page, ~u32(0) << ctx.conf.page_table_pointer_mask_bits);
+        code.mov(tmp, ctx.conf.page_table_pointer_mask);
+        code.and_(page, tmp);
     }
+    if (ctx.conf.page_table_sign_extension) {
+        code.shl(page, *ctx.conf.page_table_sign_extension);
+        code.sar(page, *ctx.conf.page_table_sign_extension);
+    }
+
     code.jz(abort, code.T_NEAR);
     if (ctx.conf.absolute_offset_page_table) {
         return page + vaddr;
     }
-    code.mov(tmp, vaddr.cvt32());
-    code.and_(tmp, static_cast<u32>(page_table_const_mask));
+    code.mov(tmp, vaddr);
+    code.and_(tmp, u32(page_table_const_mask));
     return page + tmp.cvt64();
 }
 
@@ -108,7 +122,7 @@ template<>
     const size_t unused_top_bits = 64 - ctx.conf.page_table_address_space_bits;
 
     const Xbyak::Reg64 page = ctx.reg_alloc.ScratchGpr(code);
-    const Xbyak::Reg64 tmp = ctx.conf.absolute_offset_page_table ? page : ctx.reg_alloc.ScratchGpr(code);
+    const Xbyak::Reg64 tmp = ctx.conf.absolute_offset_page_table && ctx.conf.page_table_pointer_mask == 0 ? page : ctx.reg_alloc.ScratchGpr(code);
 
     EmitDetectMisalignedVAddr(code, ctx, bitsize, abort, vaddr, tmp);
 
@@ -143,11 +157,26 @@ template<>
 
     code.shl(tmp, int(ctx.conf.page_table_log2_stride));
     code.mov(page, qword[r14 + tmp]);
-    if (ctx.conf.page_table_pointer_mask_bits == 0) {
-        code.test(page, page);
-    } else {
-        code.and_(page, ~u32(0) << ctx.conf.page_table_pointer_mask_bits);
+
+    // check for marked bit, use as unmapped if marked
+    if (ctx.conf.page_table_marked_bit) {
+        code.bt(page, *ctx.conf.page_table_marked_bit);
+        code.jc(abort, code.T_NEAR);
     }
+    // mask away attributes
+    if (ctx.conf.page_table_pointer_mask == 0) {
+        code.test(page, page);
+    } else if (std::in_range<s32>(ctx.conf.page_table_pointer_mask)) {
+        code.and_(page, ctx.conf.page_table_pointer_mask);
+    } else {
+        code.mov(tmp, ctx.conf.page_table_pointer_mask);
+        code.and_(page, tmp);
+    }
+    if (ctx.conf.page_table_sign_extension) {
+        code.shl(page, *ctx.conf.page_table_sign_extension);
+        code.sar(page, *ctx.conf.page_table_sign_extension);
+    }
+
     code.jz(abort, code.T_NEAR);
     if (ctx.conf.absolute_offset_page_table) {
         return page + vaddr;

src/dynarmic/src/dynarmic/interface/A32/config.h

@@ -159,14 +159,23 @@ struct UserConfig {
     /// Maximum size is limited by the maximum length of a x86_64 / arm64 jump.
     std::uint32_t code_cache_size = 128 * 1024 * 1024;  // bytes
 
-    /// Masks out the first N bits in host pointers from the page table.
+    /// Applies a bit mask to the bits in host pointers from the page table.
     /// The intention behind this is to allow users of Dynarmic to pack attributes in the
     /// same integer and update the pointer attribute pair atomically.
-    /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes.
-    std::int32_t page_table_pointer_mask_bits = 0;
+    /// If the configured value is ~(0b111ULL), all pointers will be forcefully aligned to 8 bytes.
+    std::uint64_t page_table_pointer_mask = 0;
 
-    // Log2 of the size per page entry, value should be either 3 or 4
-    std::size_t page_table_log2_stride = 3;
+    /// Log2 of the size per page entry, value should be either 3 or 4
+    std::uint32_t page_table_log2_stride = 3;
+
+    /// Setting this value has Dynarmic check the specified bit of the page pointer provided by page table.
+    /// If the bit is set to 1, Dynarmic will treat it as unmapped.
+    /// This bit should be included as part of `page_table_pointer_mask_bits`.
+    std::optional<std::uint8_t> page_table_marked_bit = std::nullopt;
+
+    /// If this value is set, Dynarmic will sign extend the page table pointer by this bit.
+    /// Useful for compacting bits into the page table and should be used as part of `page_table_pointer_mask`.
+    std::optional<std::uint8_t> page_table_sign_extension = std::nullopt;
 
     /// Select the architecture version to use.
     /// There are minor behavioural differences between versions.

src/dynarmic/src/dynarmic/interface/A64/config.h

@@ -173,14 +173,23 @@ struct UserConfig {
     /// This is only used if page_table is not nullptr.
     std::uint32_t page_table_address_space_bits = 36;
 
-    /// Masks out the first N bits in host pointers from the page table.
+    /// Applies a bit mask to the bits in host pointers from the page table.
     /// The intention behind this is to allow users of Dynarmic to pack attributes in the
     /// same integer and update the pointer attribute pair atomically.
-    /// If the configured value is 3, all pointers will be forcefully aligned to 8 bytes.
-    std::int32_t page_table_pointer_mask_bits = 0;
+    /// If the configured value is ~(0b111ULL), all pointers will be forcefully aligned to 8 bytes.
+    std::uint64_t page_table_pointer_mask = 0;
 
-    // Log2 of the size per page entry, value should be either 3 or 4
-    std::size_t page_table_log2_stride = 3;
+    /// Log2 of the size per page entry, value should be either 3 or 4
+    std::uint32_t page_table_log2_stride = 3;
+
+    /// Setting this value has Dynarmic check the specified bit of the page pointer provided by page table.
+    /// If the bit is set to 1, Dynarmic will treat it as unmapped.
+    /// This bit should be included as part of `page_table_pointer_mask`.
+    std::optional<std::uint8_t> page_table_marked_bit = std::nullopt;
+
+    /// If this value is set, Dynarmic will sign extend the page table pointer by this bit.
+    /// Useful for compacting bits into the page table and should be used as part of `page_table_pointer_mask`.
+    std::optional<std::uint8_t> page_table_sign_extension = std::nullopt;
 
     /// Counter-timer frequency register. The value of the register is not interpreted by
     /// dynarmic.