mirror of
https://git.eden-emu.dev/eden-emu/eden.git
synced 2026-10-06 22:10:49 +00:00
Corrections on the barriers for compute dispatch
This commit is contained in:
@@ -625,6 +625,23 @@ void RasterizerVulkan::DispatchCompute() {
|
||||
return;
|
||||
}
|
||||
|
||||
static constexpr VkMemoryBarrier2 READ_BARRIER{
|
||||
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
|
||||
.pNext = nullptr,
|
||||
.srcStageMask = vk::PIPELINE_STAGE_GRAPHICS_COMPUTE_TRANSFER,
|
||||
.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
|
||||
.dstStageMask =
|
||||
VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
|
||||
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT,
|
||||
};
|
||||
static constexpr VkMemoryBarrier2 WRITE_BARRIER{
|
||||
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
|
||||
.pNext = nullptr,
|
||||
.srcStageMask = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
|
||||
.srcAccessMask = VK_ACCESS_2_SHADER_WRITE_BIT,
|
||||
.dstStageMask = VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT | VK_PIPELINE_STAGE_2_TRANSFER_BIT,
|
||||
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT | VK_ACCESS_2_MEMORY_WRITE_BIT,
|
||||
};
|
||||
const auto& qmd{kepler_compute->launch_description};
|
||||
auto indirect_address = kepler_compute->GetIndirectComputeAddress();
|
||||
if (indirect_address) {
|
||||
@@ -639,7 +656,9 @@ void RasterizerVulkan::DispatchCompute() {
|
||||
if (!pipeline->IsBound()) {
|
||||
return;
|
||||
}
|
||||
cmdbuf.PipelineBarrier(READ_BARRIER);
|
||||
cmdbuf.DispatchIndirect(indirect_buffer, indirect_offset);
|
||||
cmdbuf.PipelineBarrier(WRITE_BARRIER);
|
||||
});
|
||||
return;
|
||||
}
|
||||
@@ -649,20 +668,13 @@ void RasterizerVulkan::DispatchCompute() {
|
||||
return;
|
||||
}
|
||||
scheduler.RequestOutsideRenderPassOperationContext();
|
||||
static constexpr VkMemoryBarrier2 READ_BARRIER{
|
||||
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
|
||||
.pNext = nullptr,
|
||||
.srcStageMask = vk::PIPELINE_STAGE_GRAPHICS_COMPUTE_TRANSFER,
|
||||
.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
|
||||
.dstStageMask = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
|
||||
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT,
|
||||
};
|
||||
scheduler.Record([](vk::CommandBuffer cmdbuf) { cmdbuf.PipelineBarrier(READ_BARRIER); });
|
||||
scheduler.Record([pipeline, dim](vk::CommandBuffer cmdbuf) {
|
||||
if (!pipeline->IsBound()) {
|
||||
return;
|
||||
}
|
||||
cmdbuf.PipelineBarrier(READ_BARRIER);
|
||||
cmdbuf.Dispatch(dim[0], dim[1], dim[2]);
|
||||
cmdbuf.PipelineBarrier(WRITE_BARRIER);
|
||||
});
|
||||
|
||||
// Log compute dispatch
|
||||
|
||||
Reference in New Issue
Block a user