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Corrections on the barriers for compute dispatch

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This commit is contained in:
CamilleLaVey
2026-09-25 04:32:48 -04:00
parent bcb3fbcf12
commit bc121efc19
1 changed files with 21 additions and 9 deletions
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src/video_core/renderer_vulkan/vk_rasterizer.cpp
+21 -9
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@@ -625,6 +625,23 @@ void RasterizerVulkan::DispatchCompute() {
return; return;
} }
static constexpr VkMemoryBarrier2 READ_BARRIER{
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
.pNext = nullptr,
.srcStageMask = vk::PIPELINE_STAGE_GRAPHICS_COMPUTE_TRANSFER,
.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
.dstStageMask =
VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT,
};
static constexpr VkMemoryBarrier2 WRITE_BARRIER{
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
.pNext = nullptr,
.srcStageMask = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
.srcAccessMask = VK_ACCESS_2_SHADER_WRITE_BIT,
.dstStageMask = VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT | VK_PIPELINE_STAGE_2_TRANSFER_BIT,
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT | VK_ACCESS_2_MEMORY_WRITE_BIT,
};
const auto& qmd{kepler_compute->launch_description}; const auto& qmd{kepler_compute->launch_description};
auto indirect_address = kepler_compute->GetIndirectComputeAddress(); auto indirect_address = kepler_compute->GetIndirectComputeAddress();
if (indirect_address) { if (indirect_address) {
@@ -639,7 +656,9 @@ void RasterizerVulkan::DispatchCompute() {
if (!pipeline->IsBound()) { if (!pipeline->IsBound()) {
return; return;
} }
cmdbuf.PipelineBarrier(READ_BARRIER);
cmdbuf.DispatchIndirect(indirect_buffer, indirect_offset); cmdbuf.DispatchIndirect(indirect_buffer, indirect_offset);
cmdbuf.PipelineBarrier(WRITE_BARRIER);
}); });
return; return;
} }
@@ -649,20 +668,13 @@ void RasterizerVulkan::DispatchCompute() {
return; return;
} }
scheduler.RequestOutsideRenderPassOperationContext(); scheduler.RequestOutsideRenderPassOperationContext();
static constexpr VkMemoryBarrier2 READ_BARRIER{
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2,
.pNext = nullptr,
.srcStageMask = vk::PIPELINE_STAGE_GRAPHICS_COMPUTE_TRANSFER,
.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT,
.dstStageMask = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT,
};
scheduler.Record([](vk::CommandBuffer cmdbuf) { cmdbuf.PipelineBarrier(READ_BARRIER); });
scheduler.Record([pipeline, dim](vk::CommandBuffer cmdbuf) { scheduler.Record([pipeline, dim](vk::CommandBuffer cmdbuf) {
if (!pipeline->IsBound()) { if (!pipeline->IsBound()) {
return; return;
} }
cmdbuf.PipelineBarrier(READ_BARRIER);
cmdbuf.Dispatch(dim[0], dim[1], dim[2]); cmdbuf.Dispatch(dim[0], dim[1], dim[2]);
cmdbuf.PipelineBarrier(WRITE_BARRIER);
}); });
// Log compute dispatch // Log compute dispatch