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reduce vaddr u64->u32

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This commit is contained in:
lizzie
2026-08-31 17:20:46 +00:00
parent be790d08f3
commit beee79a06d
3 changed files with 5 additions and 5 deletions
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src/core/arm/dynarmic/arm_dynarmic_32.cpp
+3 -3
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@@ -42,7 +42,7 @@ u64 DynarmicCallbacks32::MemoryRead64(u32 vaddr) {
std::optional<u32> DynarmicCallbacks32::MemoryReadCode(u32 vaddr) { std::optional<u32> DynarmicCallbacks32::MemoryReadCode(u32 vaddr) {
if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32)))
return std::nullopt; return std::nullopt;
auto const aligned_vaddr = vaddr & ~Core::Memory::YUZU_PAGEMASK; auto const aligned_vaddr = vaddr & u32(~Core::Memory::YUZU_PAGEMASK);
if (last_code_addr != aligned_vaddr) { if (last_code_addr != aligned_vaddr) {
m_memory.ReadBlock(aligned_vaddr, &cached_code_page, sizeof(cached_code_page)); m_memory.ReadBlock(aligned_vaddr, &cached_code_page, sizeof(cached_code_page));
last_code_addr = aligned_vaddr; last_code_addr = aligned_vaddr;
@@ -420,12 +420,12 @@ void ArmDynarmic32::SignalInterrupt(Kernel::KThread* thread) {
} }
void ArmDynarmic32::ClearInstructionCache() { void ArmDynarmic32::ClearInstructionCache() {
m_cb->last_code_addr = u64(-1); m_cb->last_code_addr = u32(-1);
m_jit->ClearCache(); m_jit->ClearCache();
} }
void ArmDynarmic32::InvalidateCacheRange(u64 addr, std::size_t size) { void ArmDynarmic32::InvalidateCacheRange(u64 addr, std::size_t size) {
m_cb->last_code_addr = u64(-1); m_cb->last_code_addr = u32(-1);
m_jit->InvalidateCacheRange(u32(addr), size); m_jit->InvalidateCacheRange(u32(addr), size);
} }
src/core/arm/dynarmic/arm_dynarmic_32.h
+1 -1
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@@ -54,7 +54,7 @@ public:
void ReturnException(u32 pc, Dynarmic::HaltReason hr); void ReturnException(u32 pc, Dynarmic::HaltReason hr);
// //
Dynarmic::CodePage cached_code_page; Dynarmic::CodePage cached_code_page;
u64 last_code_addr = u64(-1); u32 last_code_addr = u32(-1);
ArmDynarmic32& m_parent; ArmDynarmic32& m_parent;
Core::Memory::Memory& m_memory; Core::Memory::Memory& m_memory;
Kernel::KProcess* m_process{}; Kernel::KProcess* m_process{};
src/core/arm/dynarmic/arm_dynarmic_64.cpp
+1 -1
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@@ -105,7 +105,7 @@ void DynarmicCallbacks64::InstructionCacheOperationRaised(Dynarmic::A64::Instruc
last_code_addr = u64(-1); //invalidate cached page last_code_addr = u64(-1); //invalidate cached page
switch (op) { switch (op) {
case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: { case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
static constexpr u64 ICACHE_LINE_SIZE = 64; constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break; break;