Fix build

This commit is contained in:
CamilleLaVey
2026-07-03 21:21:14 -04:00
parent d7dc4f2143
commit decf41a3cb
2 changed files with 3 additions and 3 deletions
@@ -1785,7 +1785,7 @@ void RasterizerVulkan::UpdateColorWriteEnable(Tegra::Engines::Maxwell3D::Regs& r
setup_enables[index] = (mask.R || mask.G || mask.B || mask.A) ? VK_TRUE : VK_FALSE; setup_enables[index] = (mask.R || mask.G || mask.B || mask.A) ? VK_TRUE : VK_FALSE;
} }
scheduler.Record([setup_enables](vk::CommandBuffer cmdbuf) { scheduler.Record([setup_enables](vk::CommandBuffer cmdbuf) {
cmdbuf.SetColorWriteEnableEXT(0, setup_enables); cmdbuf.SetColorWriteEnableEXT(setup_enables);
}); });
} }
@@ -1590,8 +1590,8 @@ public:
dld->vkCmdSetColorWriteMaskEXT(handle, first, masks.size(), masks.data()); dld->vkCmdSetColorWriteMaskEXT(handle, first, masks.size(), masks.data());
} }
void SetColorWriteEnableEXT(u32 first, Span<VkBool32> enables) const noexcept { void SetColorWriteEnableEXT(Span<VkBool32> enables) const noexcept {
dld->vkCmdSetColorWriteEnableEXT(handle, first, enables.size(), enables.data()); dld->vkCmdSetColorWriteEnableEXT(handle, enables.size(), enables.data());
} }
void SetColorBlendEnableEXT(u32 first, Span<VkBool32> enables) const noexcept { void SetColorBlendEnableEXT(u32 first, Span<VkBool32> enables) const noexcept {