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https://git.eden-emu.dev/eden-emu/eden.git
synced 2026-08-15 21:19:47 +00:00
[TEST] Debug TICEntry shader pass
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@@ -78,11 +78,6 @@ public:
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[[nodiscard]] virtual TextureType ReadTextureType(u32 raw_handle) = 0;
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[[nodiscard]] virtual u32 ResolveBindlessHandle(u32 cbuf_index, u32 cbuf_offset,
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u32 raw_handle) {
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return raw_handle;
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}
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[[nodiscard]] virtual TexturePixelFormat ReadTexturePixelFormat(u32 raw_handle) = 0;
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[[nodiscard]] virtual bool IsTexturePixelFormatInteger(u32 raw_handle) = 0;
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@@ -502,7 +502,7 @@ u32 GetTextureHandle(Environment& env, const ConstBufferAddr& cbuf) {
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const u32 lhs_raw{env.ReadCbufValue(cbuf.index, cbuf.offset) << cbuf.shift_left};
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const u32 rhs_raw{env.ReadCbufValue(secondary_index, secondary_offset)
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<< cbuf.secondary_shift_left};
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return env.ResolveBindlessHandle(cbuf.index, cbuf.offset, lhs_raw | rhs_raw);
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return lhs_raw | rhs_raw;
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}
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[[maybe_unused]] TextureType ReadTextureType(Environment& env, const ConstBufferAddr& cbuf) {
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@@ -18,7 +18,6 @@
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#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/shader_environment.h"
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#include "video_core/shader_notify.h"
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#include "video_core/vulkan_common/vulkan_device.h"
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#include "video_core/vulkan_common/vulkan_wrapper.h"
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@@ -149,7 +148,6 @@ void ComputePipeline::Configure(Tegra::Engines::KeplerCompute& kepler_compute,
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const auto& qmd{kepler_compute.launch_description};
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const auto& cbufs{qmd.const_buffer_config};
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const bool via_header_index{qmd.linked_tsc != 0};
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const u32 tic_limit{kepler_compute.regs.tic.limit};
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const auto read_handle{[&](const auto& desc, u32 index) {
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ASSERT(((qmd.const_buffer_enable_mask >> desc.cbuf_index) & 1) != 0);
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const u32 index_offset{index << desc.size_shift};
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@@ -164,17 +162,10 @@ void ComputePipeline::Configure(Tegra::Engines::KeplerCompute& kepler_compute,
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secondary_offset};
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const u32 lhs_raw{gpu_memory.Read<u32>(addr) << desc.shift_left};
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const u32 rhs_raw{gpu_memory.Read<u32>(separate_addr) << desc.secondary_shift_left};
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const u32 combined{VideoCommon::ResolveBindlessHandleTable(
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gpu_memory, addr, lhs_raw | rhs_raw,
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TexturePair(lhs_raw | rhs_raw, via_header_index).first, tic_limit)};
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return TexturePair(combined, via_header_index);
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return TexturePair(lhs_raw | rhs_raw, via_header_index);
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}
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}
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const u32 single_raw{gpu_memory.Read<u32>(addr)};
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return TexturePair(VideoCommon::ResolveBindlessHandleTable(
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gpu_memory, addr, single_raw,
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TexturePair(single_raw, via_header_index).first, tic_limit),
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via_header_index);
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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}};
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const auto add_image{[&](const auto& desc, bool blacklist) {
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for (u32 index = 0; index < desc.count; ++index) {
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@@ -281,37 +281,17 @@ std::optional<u64> GenericEnvironment::TryFindSize() {
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return std::nullopt;
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}
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u32 ResolveBindlessHandleTable(Tegra::MemoryManager& gpu_memory, GPUVAddr record_addr,
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u32 raw_handle, u32 tic_index, u32 tic_limit) {
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static constexpr u32 HandleRecordSize = 16;
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static constexpr u32 MaxHandleTableBytes = 64 * 1024;
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if (tic_index <= tic_limit) {
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return raw_handle;
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}
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const u32 addr_low{gpu_memory.Read<u32>(record_addr)};
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const u32 addr_high{gpu_memory.Read<u32>(record_addr + 4)};
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const u32 table_size{gpu_memory.Read<u32>(record_addr + 8)};
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const GPUVAddr table_addr{(static_cast<GPUVAddr>(addr_high) << 32) |
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static_cast<GPUVAddr>(addr_low)};
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if (table_addr == 0 || table_size < HandleRecordSize || table_size > MaxHandleTableBytes) {
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return raw_handle;
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}
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const u32 count{table_size / HandleRecordSize};
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for (u32 i = 0; i < count; ++i) {
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const GPUVAddr entry_addr{table_addr + static_cast<GPUVAddr>(i) * HandleRecordSize};
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const u32 handle{gpu_memory.Read<u32>(entry_addr)};
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const u32 live{gpu_memory.Read<u32>(entry_addr + 4)};
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if (live != 0 && handle != 0 && handle <= tic_limit) {
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return handle;
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}
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}
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return raw_handle;
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}
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Tegra::Texture::TICEntry GenericEnvironment::ReadTextureInfo(GPUVAddr tic_addr, u32 tic_limit,
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bool via_header_index, u32 raw) {
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const auto handle{Tegra::Texture::TexturePair(raw, via_header_index)};
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if (handle.first > tic_limit) {
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LOG_DEBUG(Shader,
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"TIC index out of range: raw=0x{:08x} tic_index={} tsc_index={} tic_limit={} "
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"tic_addr=0x{:x} via_header_index={} stage={} program_base=0x{:x} "
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"start_address=0x{:x}",
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raw, handle.first, handle.second, tic_limit, tic_addr, via_header_index,
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static_cast<u32>(stage), program_base, start_address);
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}
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ASSERT(handle.first <= tic_limit);
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const GPUVAddr descriptor_addr{tic_addr + handle.first * sizeof(Tegra::Texture::TICEntry)};
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Tegra::Texture::TICEntry entry;
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@@ -459,24 +439,6 @@ u32 ComputeEnvironment::ReadCbufValue(u32 cbuf_index, u32 cbuf_offset) {
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return value;
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}
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u32 ComputeEnvironment::ResolveBindlessHandle(u32 cbuf_index, u32 cbuf_offset, u32 raw_handle) {
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const auto& regs{kepler_compute->regs};
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const auto& qmd{kepler_compute->launch_description};
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const auto pair{Tegra::Texture::TexturePair(raw_handle, qmd.linked_tsc != 0)};
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if (pair.first <= regs.tic.limit) {
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return raw_handle;
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}
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if (((qmd.const_buffer_enable_mask.Value() >> cbuf_index) & 1) == 0) {
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return raw_handle;
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}
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const auto& cbuf{qmd.const_buffer_config[cbuf_index]};
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if (cbuf_offset + 12 > cbuf.size) {
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return raw_handle;
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}
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return ResolveBindlessHandleTable(*gpu_memory, cbuf.Address() + cbuf_offset, raw_handle,
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pair.first, regs.tic.limit);
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}
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Shader::TextureType ComputeEnvironment::ReadTextureType(u32 handle) {
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const auto& regs{kepler_compute->regs};
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const auto& qmd{kepler_compute->launch_description};
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@@ -29,9 +29,6 @@ class Memorymanager;
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namespace VideoCommon {
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[[nodiscard]] u32 ResolveBindlessHandleTable(Tegra::MemoryManager& gpu_memory, GPUVAddr record_addr,
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u32 raw_handle, u32 tic_index, u32 tic_limit);
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class GenericEnvironment : public Shader::Environment {
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public:
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explicit GenericEnvironment() = default;
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@@ -143,8 +140,6 @@ public:
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u32 ReadCbufValue(u32 cbuf_index, u32 cbuf_offset) override;
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u32 ResolveBindlessHandle(u32 cbuf_index, u32 cbuf_offset, u32 raw_handle) override;
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Shader::TextureType ReadTextureType(u32 handle) override;
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Shader::TexturePixelFormat ReadTexturePixelFormat(u32 handle) override;
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