2026-09-11 20:06:05

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp

@@ -298,7 +298,7 @@ NvResult nvhost_gpu::AllocateObjectContext(IoctlAllocObjCtx& params) {
     return NvResult::Success;
 }
 
-static boost::container::small_vector<Tegra::CommandHeader, 512> BuildWaitCommandList(
+static std::vector<Tegra::CommandHeader> BuildWaitCommandList(
     NvFence fence) {
     return {
         Tegra::BuildCommandHeader(Tegra::BufferMethods::SyncpointPayload, 1,
@@ -310,9 +310,9 @@ static boost::container::small_vector<Tegra::CommandHeader, 512> BuildWaitComman
     };
 }
 
-static boost::container::small_vector<Tegra::CommandHeader, 512> BuildIncrementCommandList(
+static std::vector<Tegra::CommandHeader> BuildIncrementCommandList(
     NvFence fence) {
-    boost::container::small_vector<Tegra::CommandHeader, 512> result{
+    std::vector<Tegra::CommandHeader> result{
         Tegra::BuildCommandHeader(Tegra::BufferMethods::SyncpointPayload, 1,
                                   Tegra::SubmissionMode::Increasing),
         {}};
@@ -327,9 +327,9 @@ static boost::container::small_vector<Tegra::CommandHeader, 512> BuildIncrementC
     return result;
 }
 
-static boost::container::small_vector<Tegra::CommandHeader, 512> BuildIncrementWithWfiCommandList(
+static std::vector<Tegra::CommandHeader> BuildIncrementWithWfiCommandList(
     NvFence fence) {
-    boost::container::small_vector<Tegra::CommandHeader, 512> result{
+    std::vector<Tegra::CommandHeader> result{
         Tegra::BuildCommandHeader(Tegra::BufferMethods::WaitForIdle, 1,
                                   Tegra::SubmissionMode::Increasing),
         {}};

src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp

@@ -69,8 +69,8 @@ u32 A32JitState::Cpsr() const {
     cpsr |= mcl::bit::get_bit<1>(upper_location_descriptor) ? 1 << 9 : 0;
     cpsr |= mcl::bit::get_bit<0>(upper_location_descriptor) ? 1 << 5 : 0;
     // IT state
-    cpsr |= u32(upper_location_descriptor & 0b11111100'00000000);
-    cpsr |= u32(upper_location_descriptor & 0b00000011'00000000) << 17;
+    cpsr |= static_cast<u32>(upper_location_descriptor & 0b11111100'00000000);
+    cpsr |= static_cast<u32>(upper_location_descriptor & 0b00000011'00000000) << 17;
     // Other flags
     cpsr |= cpsr_jaifm;
 
@@ -169,36 +169,39 @@ constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
 u32 A32JitState::Fpscr() const {
     DEBUG_ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
 
-    const u32 fpcr_mode = u32(upper_location_descriptor) & FPSCR_MODE_MASK;
+    const u32 fpcr_mode = static_cast<u32>(upper_location_descriptor) & FPSCR_MODE_MASK;
     const u32 mxcsr = guest_MXCSR | asimd_MXCSR;
-    u32 fpscr = fpcr_mode | fpsr_nzcv;
-    fpscr |= (mxcsr & 0b0000000000001);       // IOC = IE
-    fpscr |= (mxcsr & 0b0000000111100) >> 1;  // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
-    fpscr |= fpsr_exc;
-    fpscr |= fpsr_qc != 0 ? 1 << 27 : 0;
-    return fpscr;
+
+    u32 FPSCR = fpcr_mode | fpsr_nzcv;
+    FPSCR |= (mxcsr & 0b0000000000001);       // IOC = IE
+    FPSCR |= (mxcsr & 0b0000000111100) >> 1;  // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
+    FPSCR |= fpsr_exc;
+    FPSCR |= fpsr_qc != 0 ? 1 << 27 : 0;
+
+    return FPSCR;
 }
 
-void A32JitState::SetFpscr(u32 value) {
+void A32JitState::SetFpscr(u32 FPSCR) {
     // Ensure that only upper half of upper_location_descriptor is used for FPSCR bits.
     static_assert((FPSCR_MODE_MASK & 0xFFFF0000) == FPSCR_MODE_MASK);
 
     upper_location_descriptor &= 0x0000FFFF;
-    upper_location_descriptor |= value & FPSCR_MODE_MASK;
+    upper_location_descriptor |= FPSCR & FPSCR_MODE_MASK;
 
-    fpsr_nzcv = value & FPSCR_NZCV_MASK;
-    fpsr_qc = (value >> 27) & 1;
+    fpsr_nzcv = FPSCR & FPSCR_NZCV_MASK;
+    fpsr_qc = (FPSCR >> 27) & 1;
 
     guest_MXCSR = 0x00001f80;
     asimd_MXCSR = 0x00009fc0;
 
     // RMode
-    guest_MXCSR |= ((0x6000200040000000 >> (((value >> 18) & (0x3 << 4)))) & 0xf000);
+    const std::array<u32, 4> MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000};
+    guest_MXCSR |= MXCSR_RMode[(FPSCR >> 22) & 0x3];
 
     // Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
-    fpsr_exc = value & 0x9F;
+    fpsr_exc = FPSCR & 0x9F;
 
-    if (mcl::bit::get_bit<24>(value)) {
+    if (mcl::bit::get_bit<24>(FPSCR)) {
         // VFP Flush to Zero
         guest_MXCSR |= (1 << 15);  // SSE Flush to Zero
         guest_MXCSR |= (1 << 6);   // SSE Denormals are Zero

src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.cpp

@@ -59,16 +59,16 @@ u32 A64JitState::GetFpcr() const {
 
 void A64JitState::SetFpcr(u32 value) {
     fpcr = value & FPCR_MASK;
+
     asimd_MXCSR &= 0x0000003D;
     guest_MXCSR &= 0x0000003D;
     asimd_MXCSR |= 0x00001f80;
     guest_MXCSR |= 0x00001f80;  // Mask all exceptions
+
     // RMode
-    // 0 -> 0x0000
-    // 1 -> 0x4000
-    // 2 -> 0x2000
-    // 3 -> 0x6000
-    guest_MXCSR |= ((0x6000200040000000 >> (((value >> 18) & (0x3 << 4)))) & 0xf000);
+    const std::array<u32, 4> MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000};
+    guest_MXCSR |= MXCSR_RMode[(value >> 22) & 0x3];
+
     if (mcl::bit::get_bit<24>(value)) {
         guest_MXCSR |= (1 << 15);  // SSE Flush to Zero
         guest_MXCSR |= (1 << 6);   // SSE Denormals are Zero

src/video_core/dma_pusher.h

@@ -109,11 +109,11 @@ inline CommandHeader BuildCommandHeader(BufferMethods method, u32 arg_count, Sub
 struct CommandList final {
     CommandList() = default;
     explicit CommandList(std::size_t size) : command_lists(size) {}
-    explicit CommandList(boost::container::small_vector<CommandHeader, 512>&& prefetch_command_list_)
-        : prefetch_command_list{std::move(prefetch_command_list_)} {}
-
-    boost::container::small_vector<CommandListHeader, 512> command_lists;
-    boost::container::small_vector<CommandHeader, 512> prefetch_command_list;
+    explicit CommandList(std::vector<CommandHeader>&& prefetch_command_list_)
+        : prefetch_command_list{std::move(prefetch_command_list_)}
+    {}
+    std::vector<CommandListHeader> command_lists;
+    std::vector<CommandHeader> prefetch_command_list;
 };
 
 /// @brief The DmaPusher class implements DMA submission to FIFOs, providing an area of memory that the