2026-09-14 00:57:14

Signed-off-by: lizzie <lizzie@eden-emu.dev>

.patch/ffmpeg/0001-steamdeck.patch

@@ -0,0 +1,34 @@
+diff --git a/libavutil/hwcontext_vulkan.c b/libavutil/hwcontext_vulkan.c
+index 2859ee1..766961f 100644
+--- a/libavutil/hwcontext_vulkan.c
++++ b/libavutil/hwcontext_vulkan.c
+@@ -1688,10 +1688,12 @@ static int setup_queue_families(AVHWDeviceContext *ctx, VkDeviceCreateInfo *cd)
+ 
+     hwctx->nb_qf = 0;
+     hwctx->queue_flags = 0;
++/* SD gamemode vkroots crash
+ #ifdef VK_KHR_internally_synchronized_queues
+     if (p->vkctx.extensions & FF_VK_EXT_INTERNAL_QUEUE_SYNC)
+         hwctx->queue_flags |= VK_DEVICE_QUEUE_CREATE_INTERNALLY_SYNCHRONIZED_BIT_KHR;
+ #endif
++*/
+ 
+     /* Pick each queue family to use. */
+ #define PICK_QF(type, vid_op)                                            \
+diff --git a/libavutil/vulkan.c b/libavutil/vulkan.c
+index b2e575c..5b3c9cf 100644
+--- a/libavutil/vulkan.c
++++ b/libavutil/vulkan.c
+@@ -574,10 +574,12 @@ int ff_vk_exec_pool_init(FFVulkanContext *s, AVVulkanDeviceQueueFamily *qf,
+         e->qf = qf->idx;
+         VkDeviceQueueInfo2 qinfo = {
+             .sType            = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
++/* SD gamemode vkroots crash
+ #ifdef VK_KHR_internally_synchronized_queues
+             .flags            = internal_queue_sync ?
+                                 VK_DEVICE_QUEUE_CREATE_INTERNALLY_SYNCHRONIZED_BIT_KHR : 0,
+ #endif
++*/
+             .queueFamilyIndex = qf->idx,
+             .queueIndex       = e->qi,
+         };

cpmfile.json

@@ -73,9 +73,9 @@
         "version": "v1.3.18"
     },
     "ffmpeg": {
-        "hash": "ed177621176b3961bdcaa339187d3a7688c1c8b060b79c4bb0257cbc67ad7021ae5d5adca5303b45625abbbe3d9aafdd87ce777b8690ac295290d744c875489a",
+        "hash": "68f46abf0d5dc47ab95083d59e273131a8df7948b82e62db00f00fa416e1d0bd24b799671b5a60752209bb2ac0f75295055ed0085c89a98113323cde23b69710",
         "repo": "FFmpeg/FFmpeg",
-        "version": "c7b5f1537d"
+        "version": "6efe500d2e"
     },
     "ffmpeg-ci": {
         "ci": true,

src/android/app/src/main/java/org/yuzu/yuzu_emu/dialogs/QuickSettings.kt

@@ -9,6 +9,7 @@ import android.view.LayoutInflater
 import android.view.MotionEvent
 import android.view.View
 import android.view.ViewGroup
+import android.widget.LinearLayout
 import android.widget.RadioGroup
 import android.widget.TextView
 import androidx.drawerlayout.widget.DrawerLayout
@@ -673,6 +674,167 @@ class QuickSettings(val emulationFragment: EmulationFragment) {
         }
     }
 
+    private fun addFrameGenCell(inflater: LayoutInflater, row: ViewGroup): TextView {
+        val cell = inflater.inflate(R.layout.item_quick_settings_frame_gen_cell, row, false)
+            as TextView
+        row.addView(cell)
+        return cell
+    }
+
+    fun addFrameGen(container: ViewGroup) {
+        val inflater = LayoutInflater.from(emulationFragment.requireContext())
+        val itemView = inflater.inflate(R.layout.item_quick_settings_frame_gen, container, false)
+
+        val multiplierRow = itemView.findViewById<LinearLayout>(R.id.frame_gen_multipliers)
+        val targetRow = itemView.findViewById<LinearLayout>(R.id.frame_gen_targets)
+        val targetSection = itemView.findViewById<ViewGroup>(R.id.frame_gen_target_section)
+        val flowRow = itemView.findViewById<LinearLayout>(R.id.frame_gen_flow)
+        val flowSection = itemView.findViewById<ViewGroup>(R.id.frame_gen_flow_section)
+
+        val multiplierNames =
+            emulationFragment.resources.getStringArray(R.array.frameGenMultiplierNames)
+        val multiplierValues =
+            emulationFragment.resources.getIntArray(R.array.frameGenMultiplierValues)
+        val targetValues =
+            emulationFragment.resources.getIntArray(R.array.frameGenTargetRateValues)
+        val flowValues =
+            emulationFragment.resources.getIntArray(R.array.frameGenFlowScaleValues)
+
+        val columns = maxOf(
+            multiplierValues.size + 1,
+            targetValues.size,
+            flowValues.size + 1
+        ).toFloat()
+        multiplierRow.weightSum = columns
+        targetRow.weightSum = columns
+        flowRow.weightSum = columns
+
+        val powerCell = addFrameGenCell(inflater, multiplierRow)
+
+        val multiplierCells = mutableListOf<TextView>()
+        for (name in multiplierNames) {
+            val cell = addFrameGenCell(inflater, multiplierRow)
+            cell.text = name
+            multiplierCells.add(cell)
+        }
+
+        val targetCells = mutableListOf<TextView>()
+        for (value in targetValues) {
+            val cell = addFrameGenCell(inflater, targetRow)
+            if (value == 0) {
+                cell.setText(R.string.frame_gen_fixed)
+            } else {
+                cell.text = value.toString()
+            }
+            targetCells.add(cell)
+        }
+
+        val autoCell = addFrameGenCell(inflater, flowRow)
+        autoCell.setText(R.string.frame_gen_flow_auto)
+
+        val flowCells = mutableListOf<TextView>()
+        for (value in flowValues) {
+            val cell = addFrameGenCell(inflater, flowRow)
+            cell.text = "$value%"
+            flowCells.add(cell)
+        }
+
+        val inactiveAlpha = 0.38f
+
+        fun refresh() {
+            val enabled = BooleanSetting.RENDERER_FRAME_GEN.getBoolean(needsGlobal = false)
+            val multiplier = IntSetting.RENDERER_FRAME_GEN_MULTIPLIER.getInt(needsGlobal = false)
+            val target = IntSetting.RENDERER_FRAME_GEN_TARGET_RATE.getInt(needsGlobal = false)
+            val fixed = target == 0
+            val flowAuto =
+                BooleanSetting.RENDERER_FRAME_GEN_FLOW_SCALE_AUTO.getBoolean(needsGlobal = false)
+            val flowScale = IntSetting.RENDERER_FRAME_GEN_FLOW_SCALE.getInt(needsGlobal = false)
+
+            var powerLabel = R.string.frame_gen_off
+            var rowAlpha = inactiveAlpha
+            if (enabled) {
+                powerLabel = R.string.frame_gen_on
+                rowAlpha = 1.0f
+            }
+
+            var multiplierAlpha = inactiveAlpha
+            if (enabled && fixed) {
+                multiplierAlpha = 1.0f
+            }
+
+            powerCell.setText(powerLabel)
+            powerCell.isSelected = enabled
+
+            multiplierCells.forEachIndexed { index, cell ->
+                cell.isEnabled = enabled
+                cell.isSelected = enabled && fixed && multiplierValues[index] == multiplier
+                cell.alpha = multiplierAlpha
+            }
+
+            targetSection.alpha = rowAlpha
+            targetCells.forEachIndexed { index, cell ->
+                cell.isEnabled = enabled
+                cell.isSelected = enabled && targetValues[index] == target
+            }
+
+            flowSection.alpha = rowAlpha
+            autoCell.isEnabled = enabled
+            autoCell.isSelected = enabled && flowAuto
+
+            flowCells.forEachIndexed { index, cell ->
+                cell.isEnabled = enabled
+                cell.isSelected = enabled && !flowAuto && flowValues[index] == flowScale
+            }
+        }
+
+        powerCell.setOnClickListener {
+            if (BooleanSetting.RENDERER_FRAME_GEN.getBoolean(needsGlobal = false)) {
+                BooleanSetting.RENDERER_FRAME_GEN.setBoolean(false)
+            } else {
+                IntSetting.RENDERER_FRAME_GEN_MULTIPLIER.setInt(multiplierValues.first())
+                IntSetting.RENDERER_FRAME_GEN_TARGET_RATE.setInt(0)
+                BooleanSetting.RENDERER_FRAME_GEN.setBoolean(true)
+            }
+            saveSettings()
+            refresh()
+        }
+
+        multiplierCells.forEachIndexed { index, cell ->
+            cell.setOnClickListener {
+                IntSetting.RENDERER_FRAME_GEN_MULTIPLIER.setInt(multiplierValues[index])
+                IntSetting.RENDERER_FRAME_GEN_TARGET_RATE.setInt(0)
+                saveSettings()
+                refresh()
+            }
+        }
+
+        targetCells.forEachIndexed { index, cell ->
+            cell.setOnClickListener {
+                IntSetting.RENDERER_FRAME_GEN_TARGET_RATE.setInt(targetValues[index])
+                saveSettings()
+                refresh()
+            }
+        }
+
+        autoCell.setOnClickListener {
+            BooleanSetting.RENDERER_FRAME_GEN_FLOW_SCALE_AUTO.setBoolean(true)
+            saveSettings()
+            refresh()
+        }
+
+        flowCells.forEachIndexed { index, cell ->
+            cell.setOnClickListener {
+                IntSetting.RENDERER_FRAME_GEN_FLOW_SCALE.setInt(flowValues[index])
+                BooleanSetting.RENDERER_FRAME_GEN_FLOW_SCALE_AUTO.setBoolean(false)
+                saveSettings()
+                refresh()
+            }
+        }
+
+        refresh()
+        container.addView(itemView)
+    }
+
     fun addDivider(container: ViewGroup) {
         val inflater = LayoutInflater.from(emulationFragment.requireContext())
         val dividerView = inflater.inflate(R.layout.item_quick_settings_divider, container, false)

src/android/app/src/main/java/org/yuzu/yuzu_emu/features/settings/model/BooleanSetting.kt

@@ -38,9 +38,7 @@ enum class BooleanSetting(override val key: String) : AbstractBooleanSetting {
     RENDERER_VERTEX_INPUT_DYNAMIC_STATE("vertex_input_dynamic_state"),
     RENDERER_SAMPLE_SHADING("sample_shading"),
     RENDERER_FRAME_GEN("frame_gen"),
-    RENDERER_FRAME_GEN_FP16("frame_gen_fp16"),
     RENDERER_FRAME_GEN_FLOW_SCALE_AUTO("frame_gen_flow_scale_auto"),
-    RENDERER_FRAME_GEN_DUMP_FLOW("frame_gen_dump_flow"),
     GPU_UNSWIZZLE_ENABLED("gpu_unswizzle_enabled"),
     PICTURE_IN_PICTURE("picture_in_picture"),
     USE_CUSTOM_RTC("custom_rtc_enabled"),

src/android/app/src/main/java/org/yuzu/yuzu_emu/features/settings/model/view/SettingsItem.kt

@@ -123,9 +123,7 @@ abstract class SettingsItem(
             IntSetting.RENDERER_FRAME_GEN_TARGET_RATE.key,
             IntSetting.RENDERER_FRAME_GEN_QUEUE_TARGET.key,
             BooleanSetting.RENDERER_FRAME_GEN_FLOW_SCALE_AUTO.key,
-            IntSetting.RENDERER_FRAME_GEN_FLOW_SCALE.key,
-            BooleanSetting.RENDERER_FRAME_GEN_FP16.key,
-            BooleanSetting.RENDERER_FRAME_GEN_DUMP_FLOW.key
+            IntSetting.RENDERER_FRAME_GEN_FLOW_SCALE.key
         )
 
         const val TYPE_HEADER = 0
@@ -709,20 +707,6 @@ abstract class SettingsItem(
                     units = "%"
                 )
             )
-            put(
-                SwitchSetting(
-                    BooleanSetting.RENDERER_FRAME_GEN_FP16,
-                    titleId = R.string.frame_gen_fp16,
-                    descriptionId = R.string.frame_gen_fp16_description
-                )
-            )
-            put(
-                SwitchSetting(
-                    BooleanSetting.RENDERER_FRAME_GEN_DUMP_FLOW,
-                    titleId = R.string.frame_gen_dump_flow,
-                    descriptionId = R.string.frame_gen_dump_flow_description
-                )
-            )
             put(
                 SingleChoiceSetting(
                     IntSetting.RENDERER_SCREEN_LAYOUT,

src/android/app/src/main/java/org/yuzu/yuzu_emu/features/settings/ui/SettingsFragmentPresenter.kt

@@ -124,7 +124,6 @@ class SettingsFragmentPresenter(
             ) {
                 add(IntSetting.RENDERER_FRAME_GEN_FLOW_SCALE.key)
             }
-            add(BooleanSetting.RENDERER_FRAME_GEN_FP16.key)
         }
     }
 
@@ -1553,7 +1552,6 @@ class SettingsFragmentPresenter(
                 add(BooleanSetting.DUMP_GUEST_SHADERS.key)
                 add(BooleanSetting.GPU_LOG_SHADER_DUMPS.key)
                 add(BooleanSetting.DUMP_MACROS.key)
-                add(BooleanSetting.RENDERER_FRAME_GEN_DUMP_FLOW.key)
                 add(BooleanSetting.GPU_LOG_MEMORY_TRACKING.key)
                 add(BooleanSetting.GPU_LOG_DRIVER_DEBUG.key)
                 add(IntSetting.GPU_LOG_RING_BUFFER_SIZE.key)

src/android/app/src/main/java/org/yuzu/yuzu_emu/fragments/EmulationFragment.kt

@@ -92,6 +92,7 @@ import org.yuzu.yuzu_emu.utils.GameIconUtils
 import org.yuzu.yuzu_emu.utils.GpuDriverHelper
 import org.yuzu.yuzu_emu.utils.InputHandler
 import org.yuzu.yuzu_emu.utils.Log
+import org.yuzu.yuzu_emu.utils.LosslessScalingHelper
 import org.yuzu.yuzu_emu.utils.NativeConfig
 import org.yuzu.yuzu_emu.utils.NativeFreedrenoConfig
 import org.yuzu.yuzu_emu.utils.NativePostProcessing
@@ -1188,6 +1189,11 @@ class EmulationFragment : Fragment(), SurfaceHolder.Callback {
 
             quickSettings.addDivider(container)
 
+            if (LosslessScalingHelper.isInstalled() && LosslessScalingHelper.isSupportedByGpu()) {
+                quickSettings.addFrameGen(container)
+                quickSettings.addDivider(container)
+            }
+
             quickSettings.addIntSetting(
                 R.string.renderer_accuracy,
                 container,

src/android/app/src/main/java/org/yuzu/yuzu_emu/model/Game.kt

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: 2023 yuzu Emulator Project
@@ -37,7 +37,7 @@ class Game(
 
     val settingsName: String
         get() {
-            val programIdLong = programId.toLong()
+            val programIdLong = programId.toLongOrNull() ?: 0L
             return if (programIdLong == 0L) {
                 FileUtil.getFilename(Uri.parse(path))
             } else {
@@ -47,7 +47,7 @@ class Game(
 
     val programIdHex: String
         get() {
-            val programIdLong = programId.toLong()
+            val programIdLong = programId.toLongOrNull() ?: 0L
             return if (programIdLong == 0L) {
                 "0"
             } else {

src/android/app/src/main/jni/native.cpp

@@ -1168,7 +1168,7 @@ VkPhysicalDeviceProperties GetVulkanDeviceProperties() {
     return physical_device.GetProperties();
 }
 
-bool GetVulkanMemoryModelSupport() {
+bool GetFrameGenerationSupport() {
     Common::DynamicLibrary library;
     if (!library.Open("libvulkan.so")) {
         return false;
@@ -1183,9 +1183,13 @@ bool GetVulkanMemoryModelSupport() {
 
     const Vulkan::vk::PhysicalDevice physical_device(physical_devices[0], dld);
 
+    VkPhysicalDeviceShaderFloat16Int8Features float16_int8{
+        .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES,
+        .pNext = nullptr,
+    };
     VkPhysicalDeviceVulkanMemoryModelFeatures memory_model{
         .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES,
-        .pNext = nullptr,
+        .pNext = &float16_int8,
     };
     VkPhysicalDeviceFeatures2 features{
         .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2,
@@ -1193,7 +1197,7 @@ bool GetVulkanMemoryModelSupport() {
     };
     physical_device.GetFeatures2(features);
 
-    return memory_model.vulkanMemoryModel == VK_TRUE;
+    return memory_model.vulkanMemoryModel == VK_TRUE && float16_int8.shaderFloat16 == VK_TRUE;
 }
 } // namespace
 
@@ -1272,7 +1276,7 @@ jstring Java_org_yuzu_yuzu_1emu_NativeLibrary_getVulkanApiVersion(JNIEnv* env, j
 
 jboolean Java_org_yuzu_yuzu_1emu_NativeLibrary_supportsFrameGeneration(JNIEnv* env, jobject jobj) {
     try {
-        return static_cast<jboolean>(GetVulkanMemoryModelSupport());
+        return static_cast<jboolean>(GetFrameGenerationSupport());
     } catch (...) {
         return static_cast<jboolean>(false);
     }

src/android/app/src/main/res/color/frame_gen_cell_text.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="utf-8"?>
+<selector xmlns:android="http://schemas.android.com/apk/res/android">
+    <item android:color="?attr/colorOnPrimary" android:state_selected="true" />
+    <item android:color="?attr/colorOnSurface" />
+</selector>

src/android/app/src/main/res/drawable/frame_gen_cell_background.xml

@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="utf-8"?>
+<ripple xmlns:android="http://schemas.android.com/apk/res/android"
+    android:color="?attr/colorControlHighlight">
+
+    <item android:id="@android:id/mask">
+        <shape android:shape="rectangle">
+            <solid android:color="@android:color/white" />
+            <corners android:radius="8dp" />
+        </shape>
+    </item>
+
+    <item>
+        <selector>
+            <item android:state_selected="true">
+                <shape android:shape="rectangle">
+                    <solid android:color="?attr/colorPrimary" />
+                    <corners android:radius="8dp" />
+                </shape>
+            </item>
+            <item>
+                <shape android:shape="rectangle">
+                    <corners android:radius="8dp" />
+                    <stroke
+                        android:width="1dp"
+                        android:color="?attr/colorOutline" />
+                </shape>
+            </item>
+        </selector>
+    </item>
+
+</ripple>

src/android/app/src/main/res/layout/item_quick_settings_frame_gen.xml

@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="utf-8"?>
+<LinearLayout xmlns:android="http://schemas.android.com/apk/res/android"
+    android:layout_width="match_parent"
+    android:layout_height="wrap_content"
+    android:orientation="vertical">
+
+    <LinearLayout
+        android:layout_width="match_parent"
+        android:layout_height="wrap_content"
+        android:orientation="vertical"
+        android:paddingStart="24dp"
+        android:paddingEnd="18dp"
+        android:paddingTop="12dp"
+        android:paddingBottom="8dp">
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.TitleSmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen" />
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.BodySmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="4dp"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen_quick_description"
+            android:textColor="?attr/colorOnSurfaceVariant" />
+
+        <LinearLayout
+            android:id="@+id/frame_gen_multipliers"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="10dp"
+            android:orientation="horizontal" />
+
+    </LinearLayout>
+
+    <LinearLayout
+        android:id="@+id/frame_gen_target_section"
+        android:layout_width="match_parent"
+        android:layout_height="wrap_content"
+        android:orientation="vertical"
+        android:paddingStart="24dp"
+        android:paddingEnd="18dp"
+        android:paddingTop="12dp"
+        android:paddingBottom="8dp">
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.TitleSmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen_target_rate" />
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.BodySmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="4dp"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen_target_rate_quick_description"
+            android:textColor="?attr/colorOnSurfaceVariant" />
+
+        <LinearLayout
+            android:id="@+id/frame_gen_targets"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="10dp"
+            android:orientation="horizontal" />
+
+    </LinearLayout>
+
+    <LinearLayout
+        android:id="@+id/frame_gen_flow_section"
+        android:layout_width="match_parent"
+        android:layout_height="wrap_content"
+        android:orientation="vertical"
+        android:paddingStart="24dp"
+        android:paddingEnd="18dp"
+        android:paddingTop="12dp"
+        android:paddingBottom="8dp">
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.TitleSmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen_flow_scale" />
+
+        <com.google.android.material.textview.MaterialTextView
+            style="@style/TextAppearance.Material3.BodySmall"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="4dp"
+            android:layout_marginEnd="6dp"
+            android:text="@string/frame_gen_flow_scale_quick_description"
+            android:textColor="?attr/colorOnSurfaceVariant" />
+
+        <LinearLayout
+            android:id="@+id/frame_gen_flow"
+            android:layout_width="match_parent"
+            android:layout_height="wrap_content"
+            android:layout_marginTop="10dp"
+            android:orientation="horizontal" />
+
+    </LinearLayout>
+
+</LinearLayout>

src/android/app/src/main/res/layout/item_quick_settings_frame_gen_cell.xml

@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="utf-8"?>
+<com.google.android.material.textview.MaterialTextView xmlns:android="http://schemas.android.com/apk/res/android"
+    style="@style/TextAppearance.Material3.LabelLarge"
+    android:layout_width="0dp"
+    android:layout_height="40dp"
+    android:layout_weight="1"
+    android:layout_marginEnd="6dp"
+    android:background="@drawable/frame_gen_cell_background"
+    android:clickable="true"
+    android:focusable="true"
+    android:gravity="center"
+    android:maxLines="1"
+    android:textColor="@color/frame_gen_cell_text" />

src/android/app/src/main/res/values-ar/strings.xml

@@ -305,8 +305,6 @@
     <string name="frame_gen_target_rate_60">60 إطارًا في الثانية</string>
     <string name="frame_gen_target_rate_90">90 إطارًا في الثانية</string>
     <string name="frame_gen_target_rate_120">120 إطارًا في الثانية</string>
-    <string name="frame_gen_target_rate_144">144 إطارًا في الثانية</string>
-    <string name="frame_gen_target_rate_165">165 إطارًا في الثانية</string>
     <string name="frame_gen_queue_target">هدف قائمة انتظار الإطارات</string>
     <string name="frame_gen_queue_target_description">كم عدد الإطارات المكتملة التي قد تنتظر قبل عرضها؟ تعمل قوائم الانتظار الأكبر حجمًا على امتصاص الارتفاعات المفاجئة في حمل وحدة معالجة الرسومات على حساب زمن انتقال الإدخال.</string>
     <string name="frame_gen_queue_target_0">أقل زمن انتقال (بدون تخزين مؤقت)</string>
@@ -316,10 +314,6 @@
     <string name="frame_gen_flow_scale_auto_description">قم بتقدير الحركة بناءً على الدقة التي تعرضها اللعبة فعليًّا، بدلاً من الإخراج الذي تم رفع دقته. ولا يؤثر ذلك على الدقة بأي شكل، لأن رفع الدقة لا يضيف أي تفاصيل تتعلق بالحركة.</string>
     <string name="frame_gen_flow_scale">دقة تقدير الحركة</string>
     <string name="frame_gen_flow_scale_description">دقة مسار التدفق البصري، كجزء من الناتج. ويُعد خفض هذه القيمة أرخص طريقة لاستعادة الأداء.</string>
-    <string name="frame_gen_fp16">مُظلِّلات نصف الدقة</string>
-    <string name="frame_gen_fp16_description">استخدم نسخة التظليل 16 بت. يتم التراجع تلقائيًا إلى الخيار البديل في حالة عدم توفرها في برنامج التشغيل أو الملف.</string>
-    <string name="frame_gen_dump_flow">إفراغ الإطار الذي تم إنشاؤه</string>
-    <string name="frame_gen_dump_flow_description">قم بكتابة مستويات MIP للتدفق البصري والإطار المُستكمل إلى مجلد lossless/debug مرة واحدة، لغرض استكشاف الأخطاء وإصلاحها</string>
     <string name="frame_gen_unsupported">توليد الإطار غير متاح</string>
     <string name="frame_gen_unsupported_description">لا يدعم برنامج تشغيل وحدة معالجة الرسومات هذا نموذج ذاكرة Vulkan، الذي تتطلبه برامج التظليل الخاصة بـ«Lossless Scaling».</string>
     <string name="lossless_scaling_setup_description">اختياري. قم بتوفير ملف Lossless.dll الخاص بك لتمكين إنشاء الإطارات لاحقًا</string>

src/android/app/src/main/res/values-de/strings.xml

@@ -304,8 +304,6 @@
     <string name="frame_gen_target_rate_60">60 FPS</string>
     <string name="frame_gen_target_rate_90">90 FPS</string>
     <string name="frame_gen_target_rate_120">120 FPS</string>
-    <string name="frame_gen_target_rate_144">144 FPS</string>
-    <string name="frame_gen_target_rate_165">165 FPS</string>
     <string name="frame_gen_queue_target_1">Ausbalanciert (1 Bild)</string>
     <string name="frame_gen_queue_target_2">Flüssigste (2 Bilder)</string>
     <string name="frame_gen_unsupported">Frame-Generation nicht verfügbar</string>

src/android/app/src/main/res/values-es/strings.xml

@@ -301,12 +301,9 @@
     <string name="frame_gen_target_rate_60">60 FPS</string>
     <string name="frame_gen_target_rate_90">90 FPS</string>
     <string name="frame_gen_target_rate_120">120 FPS</string>
-    <string name="frame_gen_target_rate_144">144 FPS</string>
-    <string name="frame_gen_target_rate_165">165 FPS</string>
     <string name="frame_gen_queue_target_0">Latencia más baja (Sin búfer)</string>
     <string name="frame_gen_queue_target_1">Equilibrado (1 fotograma)</string>
     <string name="frame_gen_queue_target_2">Más suave (2 fotogramas)</string>
-    <string name="frame_gen_fp16">Sombreadores de media precisión</string>
     <string name="frame_gen_unsupported">Generación de fotogramas no disponbile</string>
     <string name="lossless_scaling_install">Instalar Lossless.dll</string>
     <string name="lossless_scaling_replace_description">Seleccionar una copia diferente de Lossless.dll</string>

src/android/app/src/main/res/values-ru/strings.xml

@@ -308,10 +308,6 @@
     <string name="frame_gen_flow_scale_auto_description">Оценивать движение в разрешении, которое игра действительно рендерит, вместо масштабированного вывода. Ничего не стоит в точности, так как масштабирование не добавляет деталей движения.</string>
     <string name="frame_gen_flow_scale">Разрешение оценки движения</string>
     <string name="frame_gen_flow_scale_description">Разрешение прохода оптического потока в долях от выходного разрешения. Его понижение — самый дешёвый способ вернуть производительность.</string>
-    <string name="frame_gen_fp16">Шейдеры половинной точности</string>
-    <string name="frame_gen_fp16_description">Использовать 16-битную версию шейдеров. Автоматически переключается на обычную, если драйвер или файл не поддерживают её.</string>
-    <string name="frame_gen_dump_flow">Сохранить сгенерированный кадр</string>
-    <string name="frame_gen_dump_flow_description">Однократно записать уровни мип-карт оптического потока и интерполированный кадр в папку lossless/debug для диагностики.</string>
     <string name="frame_gen_unsupported">Генерация кадров недоступна</string>
     <string name="frame_gen_unsupported_description">Драйвер ГПУ не поддерживает модель памяти Vulkan, требуемую шейдерами Lossless Scaling.</string>
     <string name="lossless_scaling_setup_description">Опционально. Укажите свой Lossless.dll для включения генерации кадров позже.</string>

src/android/app/src/main/res/values-zh-rCN/strings.xml

@@ -305,8 +305,6 @@
     <string name="frame_gen_target_rate_60">60 FPS</string>
     <string name="frame_gen_target_rate_90">90 FPS</string>
     <string name="frame_gen_target_rate_120">120 FPS</string>
-    <string name="frame_gen_target_rate_144">144 FPS</string>
-    <string name="frame_gen_target_rate_165">165 FPS</string>
     <string name="frame_gen_queue_target">帧队列目标</string>
     <string name="frame_gen_queue_target_description">在显示之前有多少已完成渲染的帧正在等待。较大的队列可以缓解 GPU 突发的压力，但会增加输入延迟。</string>
     <string name="frame_gen_queue_target_0">最低延迟 (无缓冲)</string>
@@ -316,10 +314,6 @@
     <string name="frame_gen_flow_scale_auto_description">在游戏实际渲染的分辨率下估算运动，而不是在放大后的输出上。不会影响精确性，因为放大并不会增加运动细节。</string>
     <string name="frame_gen_flow_scale">运动预估分辨率</string>
     <string name="frame_gen_flow_scale_description">光流通道的分辨率,以输出的比例表示。降低它是提升性能最经济的做法。</string>
-    <string name="frame_gen_fp16">半精度着色器</string>
-    <string name="frame_gen_fp16_description">使用 16 位着色器变体。如果驱动或文件不支持会自动回退。</string>
-    <string name="frame_gen_dump_flow">转储已生成的帧</string>
-    <string name="frame_gen_dump_flow_description">为了排查问题，把光流 mip 级别和插值帧写入 lossless/debug 文件夹一次</string>
     <string name="frame_gen_unsupported">帧生成不可用</string>
     <string name="frame_gen_unsupported_description">这个 GPU 驱动不支持无损缩放着色器所需的 Vulkan 内存模型。</string>
     <string name="lossless_scaling_setup_description">作为可选项。请提供您自己的 Lossless.dll 以便在之后可以启用帧生成。</string>

src/android/app/src/main/res/values-zh-rTW/strings.xml

@@ -305,8 +305,6 @@
     <string name="frame_gen_target_rate_60">60 FPS</string>
     <string name="frame_gen_target_rate_90">90 FPS</string>
     <string name="frame_gen_target_rate_120">120 FPS</string>
-    <string name="frame_gen_target_rate_144">144 FPS</string>
-    <string name="frame_gen_target_rate_165">165 FPS</string>
     <string name="frame_gen_queue_target">影格佇列目標</string>
     <string name="frame_gen_queue_target_description">最多允許多少個已完成的影格在顯示器前等待，較大的佇列可以吸收 GPU 突發負載，但會增加輸入延遲</string>
     <string name="frame_gen_queue_target_0">最低延遲（無緩衝）</string>
@@ -316,10 +314,6 @@
     <string name="frame_gen_flow_scale_auto_description">以遊戲實際渲染的解析度而非升頻後的輸出進行運動預測。由於升頻後不會增加任何動態細節，因此不會影響準確度</string>
     <string name="frame_gen_flow_scale">運動預測解析度</string>
     <string name="frame_gen_flow_scale_description">光流處理的解析度，以輸出解析度的比例表示。降低此設定值是減少效能負載最有效的方法</string>
-    <string name="frame_gen_fp16">半準確著色器</string>
-    <string name="frame_gen_fp16_description">使用16位元著色器。如果驅動程式或著色器檔案不支援則會自動切換成其它版本</string>
-    <string name="frame_gen_dump_flow">傾印生成的著色器</string>
-    <string name="frame_gen_dump_flow_description">將光流的 MIP 層級與補間影格寫入 Eden 資料夾中的 lossless\debug 資料夾以便進行疑難排解</string>
     <string name="frame_gen_unsupported">無法使用影格生成</string>
     <string name="frame_gen_unsupported_description">Lossless Scaling 的著色器需要 Vulkan 記憶體模型，所選的驅動程式不支援該功能</string>
     <string name="lossless_scaling_setup_description">可選擇安裝自己擁有的 Lossless.dll 以在之後啟用影格生成功能</string>

src/android/app/src/main/res/values/arrays.xml

@@ -174,8 +174,6 @@
         <item>@string/frame_gen_target_rate_60</item>
         <item>@string/frame_gen_target_rate_90</item>
         <item>@string/frame_gen_target_rate_120</item>
-        <item>@string/frame_gen_target_rate_144</item>
-        <item>@string/frame_gen_target_rate_165</item>
     </string-array>
 
     <integer-array name="frameGenTargetRateValues">
@@ -183,8 +181,12 @@
         <item>60</item>
         <item>90</item>
         <item>120</item>
-        <item>144</item>
-        <item>165</item>
+    </integer-array>
+
+    <integer-array name="frameGenFlowScaleValues">
+        <item>50</item>
+        <item>75</item>
+        <item>100</item>
     </integer-array>
 
     <string-array name="frameGenQueueTargetNames">

src/android/app/src/main/res/values/strings.xml

@@ -331,8 +331,13 @@
     <string name="frame_gen_target_rate_60">60 FPS</string>
     <string name="frame_gen_target_rate_90">90 FPS</string>
     <string name="frame_gen_target_rate_120">120 FPS</string>
-    <string name="frame_gen_target_rate_144">144 FPS</string>
-    <string name="frame_gen_target_rate_165">165 FPS</string>
+    <string name="frame_gen_on">On</string>
+    <string name="frame_gen_off">Off</string>
+    <string name="frame_gen_fixed">Fixed</string>
+    <string name="frame_gen_flow_auto">Auto</string>
+    <string name="frame_gen_quick_description">Turn frame generation on or off and choose the frame multiplier.</string>
+    <string name="frame_gen_target_rate_quick_description">Generate frames up to a target frame rate. The multiplier adjusts on its own.</string>
+    <string name="frame_gen_flow_scale_quick_description">Resolution used to estimate motion between frames. Lower values save GPU time.</string>
     <string name="frame_gen_queue_target">Frame queue target</string>
     <string name="frame_gen_queue_target_description">How many finished frames may wait ahead of the display. Larger queues absorb GPU spikes at the cost of input latency.</string>
     <string name="frame_gen_queue_target_0">Lowest latency (Unbuffered)</string>
@@ -342,19 +347,15 @@
     <string name="frame_gen_flow_scale_auto_description">Estimate motion at the resolution the game actually renders instead of the upscaled output. Costs nothing in accuracy, since upscaling adds no motion detail.</string>
     <string name="frame_gen_flow_scale">Motion estimation resolution</string>
     <string name="frame_gen_flow_scale_description">Resolution of the optical flow pass, as a fraction of the output. Lowering it is the cheapest way to reclaim performance.</string>
-    <string name="frame_gen_fp16">Half precision shaders</string>
-    <string name="frame_gen_fp16_description">Use the 16-bit shader variant. Falls back automatically if the driver or the file lacks it.</string>
-    <string name="frame_gen_dump_flow">Dump generated frame</string>
-    <string name="frame_gen_dump_flow_description">Write the optical flow mip levels and the interpolated frame to the lossless/debug folder once, for troubleshooting</string>
     <string name="frame_gen_unsupported">Frame generation unavailable</string>
-    <string name="frame_gen_unsupported_description">This GPU driver does not support the Vulkan memory model, which the Lossless Scaling shaders require.</string>
+    <string name="frame_gen_unsupported_description">This GPU driver lacks the Vulkan memory model or half precision (float16) support that the Lossless Scaling shaders require.</string>
     <string name="lossless_scaling_setup_description">Optional. Provide your own Lossless.dll to enable frame generation later</string>
     <string name="lossless_scaling_install">Install Lossless.dll</string>
     <string name="lossless_scaling_install_description">Frame generation needs your own legal copy of Lossless.dll from Lossless Scaling</string>
     <string name="lossless_scaling_replace_description">Select a different copy of Lossless.dll</string>
     <string name="frame_generation_support">Frame generation</string>
     <string name="frame_generation_supported">Supported</string>
-    <string name="frame_generation_unsupported">Unsupported (no Vulkan memory model)</string>
+    <string name="frame_generation_unsupported">Unsupported (no Vulkan memory model or float16)</string>
     <string name="lossless_scaling">Lossless Scaling</string>
     <string name="lossless_scaling_description">Provide your own copy of Lossless.dll to enable frame generation</string>
     <string name="lossless_scaling_installed">Installed</string>

src/audio_core/adsp/apps/opus/opus_decode_object.cpp

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 

src/audio_core/adsp/apps/opus/opus_decode_object.h

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 

src/audio_core/adsp/apps/opus/opus_multistream_decode_object.h

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 

src/audio_core/adsp/apps/opus/shared_memory.h

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 

src/audio_core/sink/cubeb_sink.cpp

@@ -261,6 +261,7 @@ SinkStream* CubebSink::AcquireSinkStream(Core::System& system, u32 system_channe
     system_channels = system_channels_;
     SinkStreamPtr& stream = sink_streams.emplace_back(std::make_unique<CubebSinkStream>(
         ctx, device_channels, system_channels, output_device, input_device, name, type, system));
+    stream->SetDeviceVolume(device_volume);
 
     return stream.get();
 }
@@ -280,14 +281,11 @@ void CubebSink::CloseStreams() {
 }
 
 f32 CubebSink::GetDeviceVolume() const {
-    if (sink_streams.empty()) {
-        return 1.0f;
-    }
-
-    return sink_streams[0]->GetDeviceVolume();
+    return device_volume;
 }
 
 void CubebSink::SetDeviceVolume(f32 volume) {
+    device_volume = volume;
     for (auto& stream : sink_streams) {
         stream->SetDeviceVolume(volume);
     }

src/audio_core/sink/null_sink.h

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -38,6 +41,7 @@ public:
                                   StreamType type) override {
         if (null_sink == nullptr) {
             null_sink = std::make_unique<NullSinkStreamImpl>(system, type);
+            null_sink->SetDeviceVolume(device_volume);
         }
         return null_sink.get();
     }
@@ -45,9 +49,14 @@ public:
     void CloseStream(SinkStream*) override {}
     void CloseStreams() override {}
     f32 GetDeviceVolume() const override {
-        return 1.0f;
+        return device_volume;
+    }
+    void SetDeviceVolume(f32 volume) override {
+        device_volume = volume;
+        if (null_sink != nullptr) {
+            null_sink->SetDeviceVolume(volume);
+        }
     }
-    void SetDeviceVolume(f32 volume) override {}
     void SetSystemVolume(f32 volume) override {}
 
 private:

src/audio_core/sink/sdl3_sink.cpp

@@ -246,6 +246,7 @@ SinkStream* SDLSink::AcquireSinkStream(Core::System& system, u32 system_channels
     system_channels = system_channels_;
     SinkStreamPtr& stream = sink_streams.emplace_back(std::make_unique<SDLSinkStream>(
         device_channels, system_channels, output_device, input_device, type, system));
+    stream->SetDeviceVolume(device_volume);
     return stream.get();
 }
 
@@ -264,14 +265,11 @@ void SDLSink::CloseStreams() {
 }
 
 f32 SDLSink::GetDeviceVolume() const {
-    if (sink_streams.empty()) {
-        return 1.0f;
-    }
-
-    return sink_streams[0]->GetDeviceVolume();
+    return device_volume;
 }
 
 void SDLSink::SetDeviceVolume(f32 volume) {
+    device_volume = volume;
     for (auto& stream : sink_streams) {
         stream->SetDeviceVolume(volume);
     }

src/audio_core/sink/sink.h

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -96,6 +99,8 @@ public:
     }
 
 protected:
+    /// Master volume, persists stream lifetimes
+    f32 device_volume{1.0f};
     /// Number of device channels supported by the hardware
     u32 device_channels{2};
     /// Number of channels the game is sending

src/common/settings.h

@@ -459,7 +459,7 @@ struct Values {
                                                       &frame_gen};
 
     SwitchableSetting<u32, true> frame_gen_queue_target{linkage,
-                                                        1,
+                                                        0,
                                                         0,
                                                         2,
                                                         "frame_gen_queue_target",
@@ -469,9 +469,6 @@ struct Values {
                                                         false,
                                                         &frame_gen};
 
-    SwitchableSetting<bool> frame_gen_fp16{linkage,      true,  "frame_gen_fp16", Category::Renderer,
-                                           Specialization::Default, true, false, &frame_gen};
-
     SwitchableSetting<bool> frame_gen_dump_flow{linkage, false, "frame_gen_dump_flow",
                                                 Category::Renderer};
 

src/core/hle/service/am/display_layer_manager.cpp

@@ -73,16 +73,20 @@ Result DisplayLayerManager::CreateManagedDisplayLayer(u64* out_layer_id) {
     R_TRY(m_manager_display_service->CreateManagedLayer(
         out_layer_id, 0, display_id, Service::AppletResourceUserId{m_process->GetProcessId()}));
 
+    m_manager_display_service->SetLayerVisibility(m_visible, *out_layer_id);
+    (void)m_display_service->GetContainer()->SetLayerStackMask(*out_layer_id,
+                                                              this->GetLayerStackMask());
+
     if (m_applet_id != AppletId::Application) {
         (void)m_manager_display_service->SetLayerBlending(m_blending_enabled, *out_layer_id);
         if (m_applet_id == AppletId::OverlayDisplay) {
-            (void)m_manager_display_service->SetLayerZIndex(-1, *out_layer_id);
-            (void)m_display_service->GetContainer()->SetLayerIsOverlay(*out_layer_id, true);
+            (void)m_manager_display_service->SetLayerZIndex(Overlay, *out_layer_id);
         } else {
-            (void)m_manager_display_service->SetLayerZIndex(1, *out_layer_id);
+            (void)m_manager_display_service->SetLayerZIndex(Foreground, *out_layer_id);
         }
     }
-    (void)m_display_service->GetContainer()->SetLayerZIndex(*out_layer_id, true);
+
+    m_display_service->GetContainer()->SetLayerZIndex(*out_layer_id, true);
     m_managed_display_layers.emplace(*out_layer_id);
 
     R_SUCCEED();
@@ -122,14 +126,16 @@ Result DisplayLayerManager::IsSystemBufferSharingEnabled() {
 
     // Ensure the overlay layer is visible
     m_manager_display_service->SetLayerVisibility(m_visible, m_system_shared_layer_id);
-    m_manager_display_service->SetLayerBlending(m_blending_enabled, m_system_shared_layer_id);
-    s32 initial_z = 1;
-    (void)m_display_service->GetContainer()->SetLayerZIndex(m_system_shared_layer_id, true);
+    (void)m_manager_display_service->SetLayerBlending(m_blending_enabled, m_system_shared_layer_id);
+    s32 initial_z = Foreground;
     if (m_applet_id == AppletId::OverlayDisplay) {
-        initial_z = -1;
+        initial_z = Overlay;
+        (void)m_manager_display_service->SetLayerZIndex(initial_z, m_system_shared_layer_id);
         (void)m_display_service->GetContainer()->SetLayerIsOverlay(m_system_shared_layer_id, true);
     }
     m_manager_display_service->SetLayerZIndex(initial_z, m_system_shared_layer_id);
+    m_display_service->GetContainer()->SetLayerZIndex(m_system_shared_layer_id, true);
+    m_managed_display_layers.emplace(m_system_shared_layer_id);
     R_SUCCEED();
 }
 

src/core/hle/service/ns/read_only_application_control_data_interface.cpp

@@ -142,6 +142,7 @@ IReadOnlyApplicationControlDataInterface::IReadOnlyApplicationControlDataInterfa
         {10, &IReadOnlyApplicationControlDataInterface::ListApplicationIcon, "ListApplicationIcon"},
         {13, &IReadOnlyApplicationControlDataInterface::ListApplicationTitle, "ListApplicationTitle"},
         {19, D<&IReadOnlyApplicationControlDataInterface::GetApplicationControlData3>, "GetApplicationControlData"},
+        {23, D<&IReadOnlyApplicationControlDataInterface::GetApplicationControlData3>, "GetApplicationControlData"},
     };
     // clang-format on
 

src/core/hle/service/service.h

@@ -143,7 +143,7 @@ protected:
         /// @param expected_header_ request header in the command buffer which will trigger dispatch to this handler
         /// @param handler_callback_ member function in this service which will be called to handle the request
         /// @param name_ human-friendly name for the request. Used mostly for logging purposes.
-        constexpr FunctionInfoTyped(u32 expected_header_, HandlerFnP<T> handler_callback_, const char* name_)
+        FunctionInfoTyped(u32 expected_header_, HandlerFnP<T> handler_callback_, const char* name_)
             : FunctionInfoBase{expected_header_, HandlerFnP<ServiceFrameworkBase>(handler_callback_), name_} {}
     };
     using FunctionInfo = FunctionInfoTyped<Self>;

src/dynarmic/src/dynarmic/backend/arm64/a32_interface.cpp

@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
 
         jit_interface->is_executing = true;
@@ -42,7 +42,7 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
 
         jit_interface->is_executing = true;

src/dynarmic/src/dynarmic/backend/arm64/a64_interface.cpp

@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
         is_executing = true;
         HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
@@ -41,7 +41,7 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
         is_executing = true;
         HaltReason hr = core.Step(current_address_space, current_state, &halt_reason);

src/dynarmic/src/dynarmic/backend/arm64/abi.h

@@ -57,7 +57,7 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) {
     if (reg.is_vector()) {
         return RegisterList{1} << (reg.index() + 32);
     }
-    DEBUG_ASSERT(reg.index() != 31 && "ZR not allowed in reg list");
+    ASSERT(reg.index() != 31 && "ZR not allowed in reg list");
     if (reg.index() == -1) {
         return RegisterList{1} << 31;
     }

src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp

@@ -31,7 +31,7 @@ AddressSpace::AddressSpace(std::size_t code_cache_size)
     , code(mem.ptr(), mem.ptr())
     , fastmem_manager(exception_handler)
 {
-    DEBUG_ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
+    ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
 
     exception_handler.Register(mem, code_cache_size);
     exception_handler.SetFastmemCallback([this](u64 host_pc) {
@@ -115,13 +115,9 @@ EmittedBlockInfo AddressSpace::Emit(IR::Block block) {
 
     EmittedBlockInfo block_info = EmitArm64(code, std::move(block), GetEmitConfig(), fastmem_manager);
 
-    [[maybe_unused]] bool r = true;
-    r &= block_entries.insert({block.Location(), block_info.entry_point}).second;
-    DEBUG_ASSERT(r);
-    r &= reverse_block_entries.insert({block_info.entry_point, block.Location()}).second;
-    DEBUG_ASSERT(r);
-    r &= block_infos.insert({block_info.entry_point, block_info}).second;
-    DEBUG_ASSERT(r);
+    ASSERT(block_entries.insert({block.Location(), block_info.entry_point}).second);
+    ASSERT(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second);
+    ASSERT(block_infos.insert({block_info.entry_point, block_info}).second);
 
     Link(block_info);
     RelinkForDescriptor(block.Location(), block_info.entry_point);

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp

@@ -54,7 +54,7 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
     }
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[0].IsImmediate());
+    ASSERT(args[0].IsImmediate());
     const IR::LocationDescriptor target{args[0].GetImmediateU64()};
 
     code.LDR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr));
@@ -71,19 +71,19 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
@@ -149,13 +149,13 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }
 
 template<>
@@ -206,9 +206,9 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
     ebi.entry_point = code.xptr<CodePtr>();
 
     if (ctx.block.GetCondition() == IR::Cond::AL) {
-        DEBUG_ASSERT(!ctx.block.HasConditionFailedLocation());
+        ASSERT(!ctx.block.HasConditionFailedLocation());
     } else {
-        DEBUG_ASSERT(ctx.block.HasConditionFailedLocation());
+        ASSERT(ctx.block.HasConditionFailedLocation());
         oaknut::Label pass;
 
         pass = conf.emit_cond(code, ctx, ctx.block.GetCondition());

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp

@@ -234,7 +234,7 @@ void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
+    ASSERT(A32::IsSingleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);
 
     auto Sresult = ctx.reg_alloc.WriteS(inst);
@@ -248,7 +248,7 @@ void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     if (A32::IsDoubleExtReg(reg)) {
         const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
@@ -266,7 +266,7 @@ void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext&
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
 
     auto Dresult = ctx.reg_alloc.WriteD(inst);
@@ -294,7 +294,7 @@ void EmitIR<IR::Opcode::A32SetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
+    ASSERT(A32::IsSingleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -309,7 +309,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg));
     const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -324,7 +324,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     if (A32::IsDoubleExtReg(reg)) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp

@@ -194,8 +194,8 @@ void EmitIR<IR::Opcode::TestBit>(oaknut::CodeGenerator& code, EmitContext& ctx,
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xoperand = ctx.reg_alloc.ReadX(args[0]);
     RegAlloc::Realize(Xresult, Xoperand);
-    DEBUG_ASSERT(args[1].IsImmediate());
-    DEBUG_ASSERT(args[1].GetImmediateU8() < 64);
+    ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].GetImmediateU8() < 64);
 
     code.UBFX(Xresult, Xoperand, args[1].GetImmediateU8(), 1);
 }
@@ -893,9 +893,9 @@ static void EmitAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
 
     if (overflow_inst) {
         // There is a limited set of circumstances where this is required, so assert for this.
-        DEBUG_ASSERT(!sub);
-        DEBUG_ASSERT(!nzcv_inst);
-        DEBUG_ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false);
+        ASSERT(!sub);
+        ASSERT(!nzcv_inst);
+        ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false);
 
         auto Rb = ctx.reg_alloc.ReadReg<bitsize>(args[1]);
         auto Woverflow = ctx.reg_alloc.WriteW(overflow_inst);
@@ -1134,7 +1134,7 @@ static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* i
     if constexpr (!std::is_same_v<EmitFn2, std::nullptr_t>) {
         const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
         const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-        DEBUG_ASSERT(!(nz_inst && nzcv_inst));
+        ASSERT(!(nz_inst && nzcv_inst));
         const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
 
         if (flag_inst) {
@@ -1171,7 +1171,7 @@ template<std::size_t bitsize>
 static void EmitAndNot(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
     const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-    DEBUG_ASSERT(!(nz_inst && nzcv_inst));
+    ASSERT(!(nz_inst && nzcv_inst));
     const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -1402,7 +1402,7 @@ void EmitIR<IR::Opcode::CountLeadingZeros64>(oaknut::CodeGenerator& code, EmitCo
 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[2].IsImmediate());
+    ASSERT(args[2].IsImmediate());
 
     auto Wresult = ctx.reg_alloc.WriteW(inst);
     auto Wop1 = ctx.reg_alloc.ReadW(args[0]);
@@ -1416,7 +1416,7 @@ void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[2].IsImmediate());
+    ASSERT(args[2].IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xop1 = ctx.reg_alloc.ReadX(args[0]);
@@ -1430,7 +1430,7 @@ void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
 
     auto Wresult = ctx.reg_alloc.WriteW(inst);
     auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
@@ -1444,7 +1444,7 @@ void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xvalue = ctx.reg_alloc.ReadX(args[0]);

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp

@@ -68,7 +68,7 @@ static void EmitConvert(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst
     RegAlloc::Realize(Vto, Vfrom);
     ctx.fpsr.Load();
 
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());
+    ASSERT(rounding_mode == ctx.FPCR().RMode());
 
     emit(Vto, Vfrom);
 }
@@ -106,8 +106,8 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
             }
         }
     } else {
-        DEBUG_ASSERT(fbits == 0);
-        DEBUG_ASSERT(bitsize_to != 16);
+        ASSERT(fbits == 0);
+        ASSERT(bitsize_to != 16);
         if constexpr (is_signed) {
             switch (rounding_mode) {
             case FP::RoundingMode::ToNearest_TieEven:
@@ -449,7 +449,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
     ctx.fpsr.Load();
 
     if (exact) {
-        DEBUG_ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        ASSERT(ctx.FPCR().RMode() == rounding_mode);
         code.FRINTX(Sresult, Soperand);
     } else {
         switch (rounding_mode) {
@@ -486,7 +486,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
     ctx.fpsr.Load();
 
     if (exact) {
-        DEBUG_ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        ASSERT(ctx.FPCR().RMode() == rounding_mode);
         code.FRINTX(Dresult, Doperand);
     } else {
         switch (rounding_mode) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp

@@ -274,8 +274,8 @@ std::pair<oaknut::XReg, oaknut::XReg> InlinePageTableEmitVAddrLookup(oaknut::Cod
     code.LDR(Xscratch0, Xpagetable, Xscratch0);
 
     if (ctx.conf.page_table_marked_bit) {
-        // check for marked bit
-        code.TBNZ(Xscratch0, *ctx.conf.page_table_marked_bit, *fallback);
+        code.TST(Xscratch0, 1ULL << *ctx.conf.page_table_marked_bit);
+        code.B(NE, *fallback);
     }
 
     if (ctx.conf.page_table_pointer_mask != 0) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_packed.cpp

@@ -1,6 +1,3 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-
 /* This file is part of the dynarmic project.
  * Copyright (c) 2022 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -247,7 +244,7 @@ static void EmitPackedAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::
     }
 
     if (ge_inst) {
-        DEBUG_ASSERT(!is_halving);
+        ASSERT(!is_halving);
 
         auto Vge = ctx.reg_alloc.WriteD(ge_inst);
         RegAlloc::Realize(Vge);

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp

@@ -24,7 +24,7 @@ using namespace oaknut::util;
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    DEBUG_ASSERT(overflow_inst);
+    ASSERT(overflow_inst);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -44,7 +44,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& cod
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    DEBUG_ASSERT(overflow_inst);
+    ASSERT(overflow_inst);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -67,7 +67,7 @@ void EmitIR<IR::Opcode::SignedSaturation>(oaknut::CodeGenerator& code, EmitConte
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const std::size_t N = args[1].GetImmediateU8();
-    DEBUG_ASSERT(N >= 1 && N <= 32);
+    ASSERT(N >= 1 && N <= 32);
 
     if (N == 32) {
         ctx.reg_alloc.DefineAsExisting(inst, args[0]);
@@ -113,7 +113,7 @@ void EmitIR<IR::Opcode::UnsignedSaturation>(oaknut::CodeGenerator& code, EmitCon
     ctx.reg_alloc.SpillFlags();
 
     const std::size_t N = args[1].GetImmediateU8();
-    DEBUG_ASSERT(N <= 31);
+    ASSERT(N <= 31);
     const u32 saturated_value = (1u << N) - 1;
 
     code.MOV(Wscratch0, saturated_value);

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp

@@ -275,7 +275,7 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst,
 template<std::size_t size, typename EmitFn>
 static void EmitGetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     auto Rresult = ctx.reg_alloc.WriteReg<std::max<std::size_t>(32, size)>(inst);
@@ -310,7 +310,7 @@ void EmitIR<IR::Opcode::VectorGetElement64>(oaknut::CodeGenerator& code, EmitCon
 template<std::size_t size, typename EmitFn>
 static void EmitSetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     auto Qvector = ctx.reg_alloc.ReadWriteQ(args[0], inst);
@@ -650,7 +650,7 @@ void EmitIR<IR::Opcode::VectorExtract>(oaknut::CodeGenerator& code, EmitContext&
     auto Qa = ctx.reg_alloc.ReadQ(args[0]);
     auto Qb = ctx.reg_alloc.ReadQ(args[1]);
     const u8 position = args[2].GetImmediateU8();
-    DEBUG_ASSERT(position % 8 == 0);
+    ASSERT(position % 8 == 0);
     RegAlloc::Realize(Qresult, Qa, Qb);
 
     code.EXT(Qresult->B16(), Qa->B16(), Qb->B16(), position / 8);
@@ -663,7 +663,7 @@ void EmitIR<IR::Opcode::VectorExtractLower>(oaknut::CodeGenerator& code, EmitCon
     auto Da = ctx.reg_alloc.ReadD(args[0]);
     auto Db = ctx.reg_alloc.ReadD(args[1]);
     const u8 position = args[2].GetImmediateU8();
-    DEBUG_ASSERT(position % 8 == 0);
+    ASSERT(position % 8 == 0);
     RegAlloc::Realize(Dresult, Da, Db);
 
     code.EXT(Dresult->B8(), Da->B8(), Db->B8(), position / 8);
@@ -958,7 +958,7 @@ void EmitIR<IR::Opcode::VectorMultiply32>(oaknut::CodeGenerator& code, EmitConte
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
+    ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
     EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
         code.FMOV(Xscratch0, Qa->toD());
         code.FMOV(Xscratch1, Qb->toD());
@@ -1289,7 +1289,7 @@ void EmitIR<IR::Opcode::VectorReduceAdd64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::VectorRotateWholeVectorRight>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     EmitImmShift<8>(code, ctx, inst, [&](auto Vresult, auto Voperand, u8 shift_amount) {
-        DEBUG_ASSERT(shift_amount % 8 == 0);
+        ASSERT(shift_amount % 8 == 0);
         const u8 ext_imm = (shift_amount % 128) / 8;
         code.EXT(Vresult, Voperand, Voperand, ext_imm);
     });
@@ -1602,12 +1602,12 @@ void EmitIR<IR::Opcode::VectorSub64>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::VectorTable>(oaknut::CodeGenerator&, EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    DEBUG_ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -1674,7 +1674,7 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo
 
 template<>
 void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp

@@ -139,7 +139,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
     const u8 fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
     RegAlloc::Realize(Qto, Qfrom);
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
@@ -199,7 +199,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                 }
             }
         } else {
-            DEBUG_ASSERT(fbits == 0);
+            ASSERT(fbits == 0);
             if constexpr (is_signed) {
                 switch (rounding_mode) {
                 case FP::RoundingMode::ToNearest_TieEven:
@@ -346,7 +346,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
     const bool fpcr_controlled = args[2].GetImmediateU1();
 
     auto Qresult = ctx.reg_alloc.WriteQ(inst);
@@ -617,7 +617,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (exact) {
-            DEBUG_ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
             code.FRINTX(Qresult->S4(), Qoperand->S4());
         } else {
             switch (rounding_mode) {
@@ -657,7 +657,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (exact) {
-            DEBUG_ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
             code.FRINTX(Qresult->D2(), Qoperand->D2());
         } else {
             switch (rounding_mode) {
@@ -743,7 +743,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
     const bool fpcr_controlled = args[2].GetImmediateU1();
 
     auto Dresult = ctx.reg_alloc.WriteD(inst);

src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp

@@ -53,19 +53,19 @@ bool Argument::GetImmediateU1() const {
 
 u8 Argument::GetImmediateU8() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100);
+    ASSERT(imm < 0x100);
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x10000);
+    ASSERT(imm < 0x10000);
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100000000);
+    ASSERT(imm < 0x100000000);
     return u32(imm);
 }
 
@@ -74,12 +74,12 @@ u64 Argument::GetImmediateU64() const {
 }
 
 IR::Cond Argument::GetImmediateCond() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -92,12 +92,12 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }
 
 void HostLocInfo::SetupScratchLocation() {
-    DEBUG_ASSERT(IsCompletelyEmpty());
+    ASSERT(IsCompletelyEmpty());
     realized = true;
 }
 
 void HostLocInfo::SetupLocation(const IR::Inst* value) {
-    DEBUG_ASSERT(IsCompletelyEmpty());
+    ASSERT(IsCompletelyEmpty());
     values.clear();
     values.push_back(value);
     realized = true;
@@ -135,7 +135,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -174,11 +174,11 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,
     for (int i = 0; i < 4; i++) {
         if (args[i]) {
             if (args[i]->get().GetType() == IR::Type::U128) {
-                DEBUG_ASSERT(fprs[nsrn].IsCompletelyEmpty());
+                ASSERT(fprs[nsrn].IsCompletelyEmpty());
                 LoadCopyInto(args[i]->get().value, oaknut::QReg{nsrn});
                 nsrn++;
             } else {
-                DEBUG_ASSERT(gprs[ngrn].IsCompletelyEmpty());
+                ASSERT(gprs[ngrn].IsCompletelyEmpty());
                 LoadCopyInto(args[i]->get().value, oaknut::XReg{ngrn});
                 ngrn++;
             }
@@ -192,7 +192,7 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,
 
 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
     defined_insts.insert(inst);
-    DEBUG_ASSERT(!ValueLocation(inst));
+    ASSERT(!ValueLocation(inst));
 
     if (arg.value.IsImmediate()) {
         inst->ReplaceUsesWith(arg.value);
@@ -206,9 +206,9 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 
 void RegAlloc::DefineAsRegister(IR::Inst* inst, oaknut::Reg reg) {
     defined_insts.insert(inst);
-    DEBUG_ASSERT(!ValueLocation(inst));
+    ASSERT(!ValueLocation(inst));
     auto& info = reg.is_vector() ? fprs[reg.index()] : gprs[reg.index()];
-    DEBUG_ASSERT(info.IsCompletelyEmpty());
+    ASSERT(info.IsCompletelyEmpty());
     info.values.push_back(inst);
     info.expected_uses += inst->UseCount();
 }
@@ -228,18 +228,18 @@ void RegAlloc::UpdateAllUses() {
 
 void RegAlloc::AssertAllUnlocked() const {
     const auto is_unlocked = [](const auto& i) { return !i.locked && !i.realized; };
-    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
-    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
-    DEBUG_ASSERT(is_unlocked(flags));
-    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked));
+    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
+    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
+    ASSERT(is_unlocked(flags));
+    ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked));
 }
 
 void RegAlloc::AssertNoMoreUses() const {
     const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    DEBUG_ASSERT(is_empty(flags));
-    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    ASSERT(is_empty(flags));
+    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
 }
 
 void RegAlloc::EmitVerboseDebuggingOutput() {
@@ -271,7 +271,7 @@ void RegAlloc::EmitVerboseDebuggingOutput() {
 
 template<HostLoc::Kind kind>
 int RegAlloc::GenerateImmediate(const IR::Value& value) {
-    DEBUG_ASSERT(value.GetType() != IR::Type::U1);
+    ASSERT(value.GetType() != IR::Type::U1);
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
         SpillGpr(new_location_index);
@@ -309,15 +309,15 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
 
     if (current_location->kind == required_kind) {
         ValueInfo(*current_location).realized = true;
         return current_location->index;
     }
 
-    DEBUG_ASSERT(!bool(ValueInfo(*current_location).realized));
-    DEBUG_ASSERT(bool(ValueInfo(*current_location).locked));
+    ASSERT(!bool(ValueInfo(*current_location).realized));
+    ASSERT(bool(ValueInfo(*current_location).locked));
 
     if constexpr (required_kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -328,7 +328,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
             UNREACHABLE(); //logic error
         case HostLoc::Kind::Fpr:
             code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
-            // DEBUG_ASSERT size fits
+            // ASSERT size fits
             break;
         case HostLoc::Kind::Spill:
             code.LDR(oaknut::XReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
@@ -355,7 +355,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
             code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
             break;
         case HostLoc::Kind::Flags:
-            DEBUG_ASSERT(false && "Moving from flags into fprs is not currently supported");
+            ASSERT(false && "Moving from flags into fprs is not currently supported");
             break;
         }
 
@@ -372,7 +372,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
 template<HostLoc::Kind kind>
 int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
     defined_insts.insert(value);
-    DEBUG_ASSERT(!ValueLocation(value));
+    ASSERT(!ValueLocation(value));
 
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -407,7 +407,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
         LoadCopyInto(read_value, oaknut::QReg{write_loc});
         return write_loc;
     } else if constexpr (kind == HostLoc::Kind::Flags) {
-        DEBUG_ASSERT(false && "Incorrect function for ReadWrite of flags");
+        ASSERT(false && "Incorrect function for ReadWrite of flags");
     } else {
         UNREACHABLE();
     }
@@ -439,7 +439,7 @@ int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }
 
 void RegAlloc::SpillGpr(int index) {
-    DEBUG_ASSERT(!gprs[index].locked && !gprs[index].realized);
+    ASSERT(!gprs[index].locked && !gprs[index].realized);
     if (gprs[index].values.empty()) {
         return;
     }
@@ -449,7 +449,7 @@ void RegAlloc::SpillGpr(int index) {
 }
 
 void RegAlloc::SpillFpr(int index) {
-    DEBUG_ASSERT(!fprs[index].locked && !fprs[index].realized);
+    ASSERT(!fprs[index].locked && !fprs[index].realized);
     if (fprs[index].values.empty()) {
         return;
     }
@@ -461,7 +461,7 @@ void RegAlloc::SpillFpr(int index) {
 void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
     defined_insts.insert(write);
     const auto current_location = ValueLocation(read.value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
 
     if (current_location->kind == HostLoc::Kind::Flags) {
         if (!flags.IsOneRemainingUse()) {
@@ -489,7 +489,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
 }
 
 void RegAlloc::SpillFlags() {
-    DEBUG_ASSERT(!flags.locked && !flags.realized);
+    ASSERT(!flags.locked && !flags.realized);
     if (flags.values.empty()) {
         return;
     }
@@ -501,7 +501,7 @@ void RegAlloc::SpillFlags() {
 
 int RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    DEBUG_ASSERT(iter != spills.end() && "All spill locations are full");
+    ASSERT(iter != spills.end() && "All spill locations are full");
     return static_cast<int>(iter - spills.begin());
 }
 
@@ -512,14 +512,14 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::XReg reg) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
     switch (current_location->kind) {
     case HostLoc::Kind::Gpr:
         code.MOV(reg, oaknut::XReg{current_location->index});
         break;
     case HostLoc::Kind::Fpr:
         code.FMOV(reg, oaknut::DReg{current_location->index});
-        // DEBUG_ASSERT size fits
+        // ASSERT size fits
         break;
     case HostLoc::Kind::Spill:
         code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
@@ -538,7 +538,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
     switch (current_location->kind) {
     case HostLoc::Kind::Gpr:
         code.FMOV(reg.toD(), oaknut::XReg{current_location->index});

src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp

@@ -87,11 +87,7 @@ private:
 };
 
 MachHandler::MachHandler() {
-#define KCHECK(x) do { \
-        [[maybe_unused]] auto r = (x); \
-        DEBUG_ASSERT(r == KERN_SUCCESS && "init failure at " #x); \
-    } while (0);
-
+#define KCHECK(x) ASSERT((x) == KERN_SUCCESS && "init failure at " #x)
     KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port));
     KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND));
     KCHECK(task_set_exception_ports(mach_task_self(), EXC_MASK_BAD_ACCESS, server_port, EXCEPTION_STATE | MACH_EXCEPTION_CODES, THREAD_STATE));

src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp

@@ -138,7 +138,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
 #elif defined(ARCHITECTURE_loongarch64)
             CTX_PC = fc.call_pc;
 #else
-            DEBUG_ASSERT(false);
+            ASSERT(false);
 #endif
             return;
         }

src/dynarmic/src/dynarmic/backend/loongarch64/a32_address_space.cpp

@@ -115,7 +115,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
             break;
         }
         default:
-            DEBUG_ASSERT(false && "Invalid relocation target");
+            ASSERT(false && "Invalid relocation target");
         }
     }
 }

src/dynarmic/src/dynarmic/backend/loongarch64/a32_interface.cpp

@@ -25,7 +25,7 @@ struct Jit::Impl final {
             , current_address_space(conf) {}
 
     HaltReason Run() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         jit_interface->is_executing = true;
 
         const auto location_descriptor = current_state.GetLocationDescriptor();
@@ -38,7 +38,7 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         jit_interface->is_executing = true;
 
         const auto location_descriptor = A32::LocationDescriptor{current_state.GetLocationDescriptor()}.SetSingleStepping(true);

src/dynarmic/src/dynarmic/backend/loongarch64/code_block.h

@@ -20,7 +20,7 @@ public:
     explicit CodeBlock(std::size_t size) noexcept
             : memsize(size) {
         mem = static_cast<u8*>(mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0));
-        DEBUG_ASSERT(mem != MAP_FAILED);
+        ASSERT(mem != MAP_FAILED);
         la_init_assembler(&as, mem, size);
     }
 

src/dynarmic/src/dynarmic/backend/loongarch64/emit_loongarch64.cpp

@@ -16,7 +16,7 @@ namespace Dynarmic::Backend::LoongArch64 {
 
 template<IR::Opcode op>
 void EmitIR(lagoon_assembler_t&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented opcode");
+    ASSERT(false && "Unimplemented opcode");
 }
 
 template<>
@@ -36,7 +36,7 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t&, EmitContext& ct
 
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }
 
 template<>
@@ -98,7 +98,7 @@ EmittedBlockInfo EmitLoongArch64(lagoon_assembler_t& as, IR::Block block, const
     const auto term = block.GetTerminal();
     const IR::Term::LeafTerminal* leaft_term = std::get_if<IR::Term::LeafTerminal>(&term);
     const IR::Term::LinkBlock* link_block_term = std::get_if<IR::Term::LinkBlock>(leaft_term);
-    DEBUG_ASSERT(link_block_term);
+    ASSERT(link_block_term);
     la_load_immediate64(&as, Xscratch0, link_block_term->next.Value());
     la_st_w(&as, Xscratch0, Xstate, static_cast<int32_t>(offsetof(A32JitState, regs) + sizeof(u32) * 15));
 

src/dynarmic/src/dynarmic/backend/loongarch64/emit_loongarch64_a32.cpp

@@ -41,7 +41,7 @@ template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZC>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
-    DEBUG_ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
+    ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
 
     auto Xnz = ctx.reg_alloc.ReadX(args[0]);
     auto Xc = ctx.reg_alloc.ReadX(args[1]);

src/dynarmic/src/dynarmic/backend/loongarch64/emit_loongarch64_data_processing.cpp

@@ -22,8 +22,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t& as, EmitContext&
     auto& shift_arg = args[1];
     auto& carry_arg = args[2];
 
-    DEBUG_ASSERT(carry_inst != nullptr);
-    DEBUG_ASSERT(shift_arg.IsImmediate());
+    ASSERT(carry_inst != nullptr);
+    ASSERT(shift_arg.IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);

src/dynarmic/src/dynarmic/backend/loongarch64/reg_alloc.cpp

@@ -42,19 +42,19 @@ bool Argument::GetImmediateU1() const {
 
 u8 Argument::GetImmediateU8() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100);
+    ASSERT(imm < 0x100);
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x10000);
+    ASSERT(imm < 0x10000);
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100000000);
+    ASSERT(imm < 0x100000000);
     return u32(imm);
 }
 
@@ -63,12 +63,12 @@ u64 Argument::GetImmediateU64() const {
 }
 
 IR::Cond Argument::GetImmediateCond() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -77,7 +77,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }
 
 void HostLocInfo::SetupScratchLocation() {
-    DEBUG_ASSERT(IsCompletelyEmpty());
+    ASSERT(IsCompletelyEmpty());
     locked = 1;
     realized = true;
 }
@@ -103,7 +103,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -121,7 +121,7 @@ void RegAlloc::UpdateAllUses() {
 }
 
 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
-    DEBUG_ASSERT(!ValueLocation(inst));
+    ASSERT(!ValueLocation(inst));
 
     if (arg.value.IsImmediate()) {
         inst->ReplaceUsesWith(arg.value);
@@ -136,7 +136,7 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 void RegAlloc::AssertNoMoreUses() const {
     // TODO: Re-enable this assert once all register allocation issues are fixed
     // const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    // DEBUG_ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
+    // ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
 }
 
 template<HostLoc::Kind kind>
@@ -151,7 +151,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
 
         return new_location_index;
     } else if constexpr (kind == HostLoc::Kind::Fpr) {
-        DEBUG_ASSERT(false && "Unimplemented instruction");
+        ASSERT(false && "Unimplemented instruction");
     } else {
         UNREACHABLE();
     }
@@ -165,15 +165,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
 
     if (current_location->kind == required_kind) {
         ValueInfo(*current_location).realized = true;
         return current_location->index;
     }
 
-    DEBUG_ASSERT(!ValueInfo(*current_location).realized);
-    DEBUG_ASSERT(!ValueInfo(*current_location).locked);
+    ASSERT(!ValueInfo(*current_location).realized);
+    ASSERT(!ValueInfo(*current_location).locked);
 
     if constexpr (required_kind == HostLoc::Kind::Gpr) {
         const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
@@ -236,7 +236,7 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kin
         }
     }
 
-    DEBUG_ASSERT(!ValueLocation(value));
+    ASSERT(!ValueLocation(value));
 
     const auto setup_location = [&](HostLocInfo& info) {
         info = {};
@@ -277,7 +277,7 @@ u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset
     std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) {
         return !hostloc_info[base_offset + i].locked;
     });
-    DEBUG_ASSERT(!candidates.empty());
+    ASSERT(!candidates.empty());
 
     u32 best = candidates[0];
     size_t min_lru = hostloc_info[base_offset + best].lru_counter;
@@ -294,7 +294,7 @@ u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset
 
 void RegAlloc::SpillGpr(u32 index) {
     auto& gpr_info = hostloc_info[GprOffset + index];
-    DEBUG_ASSERT(!gpr_info.locked && !gpr_info.realized);
+    ASSERT(!gpr_info.locked && !gpr_info.realized);
     if (gpr_info.values.empty()) {
         return;
     }
@@ -306,7 +306,7 @@ void RegAlloc::SpillGpr(u32 index) {
 
 void RegAlloc::SpillFpr(u32 index) {
     auto& fpr_info = hostloc_info[FprOffset + index];
-    DEBUG_ASSERT(!fpr_info.locked && !fpr_info.realized);
+    ASSERT(!fpr_info.locked && !fpr_info.realized);
     if (fpr_info.values.empty()) {
         return;
     }

src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp

@@ -94,7 +94,7 @@ void A32AddressSpace::EmitPrelude() {
 
 void A32AddressSpace::SetCursorPtr(CodePtr ptr) {
     ptrdiff_t offset = ptr - GetMemPtr<CodePtr>();
-    DEBUG_ASSERT(offset >= 0);
+    ASSERT(offset >= 0);
     as.RewindBuffer(offset);
 }
 

src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp

@@ -31,7 +31,7 @@ struct Jit::Impl final {
             , core(conf) {}
 
     HaltReason Run() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         jit_interface->is_executing = true;
         HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
         RequestCacheInvalidation();
@@ -40,9 +40,9 @@ struct Jit::Impl final {
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         jit_interface->is_executing = true;
-        DEBUG_ASSERT(false && "Unimplemented instruction");
+        ASSERT(false && "Unimplemented instruction");
         RequestCacheInvalidation();
         jit_interface->is_executing = false;
         return HaltReason{};

src/dynarmic/src/dynarmic/backend/riscv64/a64_interface.cpp

@@ -28,12 +28,12 @@ struct Jit::Impl final {
         , jit_interface(jit_interface) {}
 
     HaltReason Run() {
-        DEBUG_ASSERT(false);
+        ASSERT(false);
         return HaltReason{};
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(false);
+        ASSERT(false);
         return HaltReason{};
     }
 
@@ -51,7 +51,7 @@ struct Jit::Impl final {
     }
 
     void Reset() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         //jit_state = {};
     }
 

src/dynarmic/src/dynarmic/backend/riscv64/code_block.h

@@ -22,7 +22,7 @@ class CodeBlock {
 public:
     explicit CodeBlock(std::size_t size) noexcept : memsize(size) {
         mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
-        DEBUG_ASSERT(mem != nullptr);
+        ASSERT(mem != nullptr);
     }
 
     ~CodeBlock() noexcept {

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp

@@ -35,39 +35,39 @@ void EmitIR<IR::Opcode::Identity>(biscuit::Assembler&, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Breakpoint>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CallHostFunction>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PushRSB>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }
 
 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::GetNZCVFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
     [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }
 
 template<>
@@ -87,12 +87,12 @@ void EmitIR<IR::Opcode::GetNZFromOp>(biscuit::Assembler& as, EmitContext& ctx, I
 
 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -109,7 +109,7 @@ void EmitIR<IR::Opcode::GetCFlagFromNZCV>(biscuit::Assembler& as, EmitContext& c
 
 template<>
 void EmitIR<IR::Opcode::NZCVFromPackedFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitConfig& emit_conf) {

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp

@@ -228,7 +228,7 @@ void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx) {
 
 template<>
 void EmitIR<IR::Opcode::A32SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -243,17 +243,17 @@ void EmitIR<IR::Opcode::A32GetRegister>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -272,27 +272,27 @@ void EmitIR<IR::Opcode::A32SetRegister>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -307,17 +307,17 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -325,7 +325,7 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     // TODO: Add full implementation
-    DEBUG_ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
+    ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
 
     auto Xnz = ctx.reg_alloc.ReadX(args[0]);
     auto Xc = ctx.reg_alloc.ReadX(args[1]);
@@ -341,82 +341,82 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
 
 template<>
 void EmitIR<IR::Opcode::A32GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32OrQFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetGEFlagsCompressed>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32BXWritePC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32UpdateUpperLocationDescriptor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32GetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_coprocessor.cpp

@@ -22,37 +22,37 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocInternalOperation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocSendOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocGetOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocLoadWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32CoprocStoreWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32_memory.cpp

@@ -22,87 +22,87 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A32ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64.cpp

@@ -22,182 +22,182 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A64SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetPC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64InstructionCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCNTFRQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCNTPCT>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetCTR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetDCZID>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64GetTPIDRRO>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64SetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a64_memory.cpp

@@ -22,107 +22,107 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::A64ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64WriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_cryptography.cpp

@@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CRC32ISO64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AESDecryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AESEncryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AESInverseMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AESMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256Hash>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule0>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule1>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp

@@ -22,67 +22,67 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::Pack2x32To1x64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Pack2x64To1x128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LeastSignificantByte>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MostSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MostSignificantBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::IsZero32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::IsZero64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::TestBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelect32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelect64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ConditionalSelectNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -95,8 +95,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&
     auto& carry_arg = args[2];
 
     // TODO: Add full implementation
-    DEBUG_ASSERT(carry_inst != nullptr);
-    DEBUG_ASSERT(shift_arg.IsImmediate());
+    ASSERT(carry_inst != nullptr);
+    ASSERT(shift_arg.IsImmediate());
 
     auto Xresult = ctx.reg_alloc.WriteX(inst);
     auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);
@@ -124,7 +124,7 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -136,8 +136,8 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext
     auto& shift_arg = args[1];
 
     // TODO: Add full implementation
-    DEBUG_ASSERT(carry_inst == nullptr);
-    DEBUG_ASSERT(shift_arg.IsImmediate());
+    ASSERT(carry_inst == nullptr);
+    ASSERT(shift_arg.IsImmediate());
 
     const u8 shift = shift_arg.GetImmediateU8();
     auto Xresult = ctx.reg_alloc.WriteX(inst);
@@ -153,72 +153,72 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::BitRotateRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::BitRotateRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightExtended>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::RotateRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<size_t bitsize>
@@ -264,7 +264,7 @@ static void AddImmWithFlags(biscuit::Assembler& as, biscuit::GPR rd, biscuit::GP
         as.SLLI(Xscratch1, Xscratch1, 28);
         as.OR(flags, flags, Xscratch1);
     } else {
-        DEBUG_ASSERT(false && "Unimplemented instruction");
+        ASSERT(false && "Unimplemented instruction");
     }
 }
 
@@ -279,7 +279,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
     auto Xa = ctx.reg_alloc.ReadX(args[0]);
 
     if (overflow_inst) {
-        DEBUG_ASSERT(false && "Unimplemented instruction");
+        ASSERT(false && "Unimplemented instruction");
     } else if (nzcv_inst) {
         if (args[1].IsImmediate()) {
             const u64 imm = args[1].GetImmediateU64();
@@ -294,17 +294,17 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                     AddImmWithFlags<bitsize>(as, *Xresult, *Xa, sub ? -imm : imm, *Xflags);
                 }
             } else {
-                DEBUG_ASSERT(false && "Unimplemented instruction");
+                ASSERT(false && "Unimplemented instruction");
             }
         } else {
-            DEBUG_ASSERT(false && "Unimplemented instruction");
+            ASSERT(false && "Unimplemented instruction");
         }
     } else {
         if (args[1].IsImmediate()) {
             const u64 imm = args[1].GetImmediateU64();
 
             if (args[2].IsImmediate()) {
-                DEBUG_ASSERT(false && "Unimplemented instruction");
+                ASSERT(false && "Unimplemented instruction");
             } else {
                 auto Xnzcv = ctx.reg_alloc.ReadX(args[2]);
                 RegAlloc::Realize(Xresult, Xa, Xnzcv);
@@ -317,7 +317,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                 as.ADDW(Xresult, Xa, Xscratch0);
             }
         } else {
-            DEBUG_ASSERT(false && "Unimplemented instruction");
+            ASSERT(false && "Unimplemented instruction");
         }
     }
 }
@@ -329,7 +329,7 @@ void EmitIR<IR::Opcode::Add32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Add64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
@@ -339,237 +339,237 @@ void EmitIR<IR::Opcode::Sub32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins
 
 template<>
 void EmitIR<IR::Opcode::Sub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Mul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Mul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::And32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::And64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AndNot32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::AndNot64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Eor32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Eor64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Or32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Or64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Not32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::Not64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ZeroExtendLongToQuad>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ByteReverseDual>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MaxUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MinSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MinSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MinUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::MinUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_floating_point.cpp

@@ -22,442 +22,442 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::FPAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPCompare32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPCompare64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipExponent64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_packed.cpp

@@ -22,172 +22,172 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::PackedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedAbsDiffSumU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::PackedSelect>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_saturation.cpp

@@ -22,112 +22,112 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_floating_point.cpp

@@ -22,337 +22,337 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreater32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreater64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_vector_saturation.cpp

@@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    DEBUG_ASSERT(false && "Unimplemented instruction");
+    ASSERT(false && "Unimplemented instruction");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp

@@ -44,19 +44,19 @@ bool Argument::GetImmediateU1() const {
 
 u8 Argument::GetImmediateU8() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100);
+    ASSERT(imm < 0x100);
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x10000);
+    ASSERT(imm < 0x10000);
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm < 0x100000000);
+    ASSERT(imm < 0x100000000);
     return u32(imm);
 }
 
@@ -65,12 +65,12 @@ u64 Argument::GetImmediateU64() const {
 }
 
 IR::Cond Argument::GetImmediateCond() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -79,7 +79,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }
 
 void HostLocInfo::SetupScratchLocation() {
-    DEBUG_ASSERT(IsCompletelyEmpty());
+    ASSERT(IsCompletelyEmpty());
     realized = true;
 }
 
@@ -104,7 +104,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -128,7 +128,7 @@ void RegAlloc::UpdateAllUses() {
 }
 
 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
-    DEBUG_ASSERT(!ValueLocation(inst));
+    ASSERT(!ValueLocation(inst));
 
     if (arg.value.IsImmediate()) {
         inst->ReplaceUsesWith(arg.value);
@@ -142,15 +142,15 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 
 void RegAlloc::AssertNoMoreUses() const {
     const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
 }
 
 template<HostLoc::Kind kind>
 u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
     // TODO
-    // DEBUG_ASSERT(value.GetType() != IR::Type::U1);
+    // ASSERT(value.GetType() != IR::Type::U1);
 
     if constexpr (kind == HostLoc::Kind::Gpr) {
         const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -161,7 +161,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
 
         return new_location_index;
     } else if constexpr (kind == HostLoc::Kind::Fpr) {
-        DEBUG_ASSERT(false && "Unimplemented instruction");
+        ASSERT(false && "Unimplemented instruction");
     } else {
         UNREACHABLE();
     }
@@ -175,15 +175,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
     }
 
     const auto current_location = ValueLocation(value.GetInst());
-    DEBUG_ASSERT(current_location);
+    ASSERT(current_location);
 
     if (current_location->kind == required_kind) {
         ValueInfo(*current_location).realized = true;
         return current_location->index;
     }
 
-    DEBUG_ASSERT(!ValueInfo(*current_location).realized);
-    DEBUG_ASSERT(!ValueInfo(*current_location).locked);
+    ASSERT(!ValueInfo(*current_location).realized);
+    ASSERT(!ValueInfo(*current_location).locked);
 
     if constexpr (required_kind == HostLoc::Kind::Gpr) {
         const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -194,7 +194,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
             UNREACHABLE(); //logic error
         case HostLoc::Kind::Fpr:
             as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
-            // DEBUG_ASSERT size fits
+            // ASSERT size fits
             break;
         case HostLoc::Kind::Spill:
             as.LD(biscuit::GPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
@@ -229,7 +229,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
 template<HostLoc::Kind required_kind>
 u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
-    DEBUG_ASSERT(!ValueLocation(value));
+    ASSERT(!ValueLocation(value));
 
     const auto setup_location = [&](HostLocInfo& info) {
         info = {};
@@ -274,7 +274,7 @@ u32 RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }
 
 void RegAlloc::SpillGpr(u32 index) {
-    DEBUG_ASSERT(!gprs[index].locked && !gprs[index].realized);
+    ASSERT(!gprs[index].locked && !gprs[index].realized);
     if (gprs[index].values.empty()) {
         return;
     }
@@ -284,7 +284,7 @@ void RegAlloc::SpillGpr(u32 index) {
 }
 
 void RegAlloc::SpillFpr(u32 index) {
-    DEBUG_ASSERT(!fprs[index].locked && !fprs[index].realized);
+    ASSERT(!fprs[index].locked && !fprs[index].realized);
     if (fprs[index].values.empty()) {
         return;
     }
@@ -295,7 +295,7 @@ void RegAlloc::SpillFpr(u32 index) {
 
 u32 RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    DEBUG_ASSERT(iter != spills.end() && "All spill locations are full");
+    ASSERT(iter != spills.end() && "All spill locations are full");
     return static_cast<u32>(iter - spills.begin());
 }
 

src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp

@@ -209,11 +209,11 @@ void A32EmitX64::InvalidateCacheRanges(const boost::icl::interval_set<u32>& rang
 
 void A32EmitX64::EmitCondPrelude(const A32EmitContext& ctx) {
     if (ctx.block.GetCondition() == IR::Cond::AL) {
-        DEBUG_ASSERT(!ctx.block.HasConditionFailedLocation());
+        ASSERT(!ctx.block.HasConditionFailedLocation());
         return;
     }
 
-    DEBUG_ASSERT(ctx.block.HasConditionFailedLocation());
+    ASSERT(ctx.block.HasConditionFailedLocation());
 
     Xbyak::Label pass = EmitCond(ctx.block.GetCondition());
     if (conf.enable_cycle_counting) {
@@ -311,7 +311,7 @@ void A32EmitX64::EmitA32GetRegister(A32EmitContext& ctx, IR::Inst* inst) {
 
 void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
+    ASSERT(A32::IsSingleExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     code.movss(result, MJitStateExtReg(reg));
@@ -320,7 +320,7 @@ void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins
 
 void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     code.movsd(result, MJitStateExtReg(reg));
@@ -329,7 +329,7 @@ void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins
 
 void A32EmitX64::EmitA32GetVector(A32EmitContext& ctx, IR::Inst* inst) {
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     if (A32::IsDoubleExtReg(reg)) {
@@ -358,7 +358,7 @@ void A32EmitX64::EmitA32SetRegister(A32EmitContext& ctx, IR::Inst* inst) {
 void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
+    ASSERT(A32::IsSingleExtReg(reg));
 
     if (args[1].IsInXmm(ctx.reg_alloc)) {
         Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -372,7 +372,7 @@ void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg));
 
     if (args[1].IsInXmm(ctx.reg_alloc)) {
         const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -386,7 +386,7 @@ void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetVector(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
 
     const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
     if (A32::IsDoubleExtReg(reg)) {
@@ -647,7 +647,7 @@ void A32EmitX64::EmitA32GetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {
 
 void A32EmitX64::EmitA32SetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(!args[0].IsImmediate());
+    ASSERT(!args[0].IsImmediate());
 
     if (args[0].IsInXmm(ctx.reg_alloc)) {
         const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[0]);
@@ -788,7 +788,7 @@ void A32EmitX64::EmitA32ExceptionRaised(A32EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.EndOfAllocScope();
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
     const u32 pc = args[0].GetImmediateU32();
     const u64 exception = args[1].GetImmediateU64();
     Devirtualize<&A32::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {

src/dynarmic/src/dynarmic/backend/x64/a32_interface.cpp

@@ -74,7 +74,7 @@ struct Jit::Impl {
     ~Impl() = default;
 
     HaltReason Run() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         jit_interface->is_executing = true;
         const CodePtr current_codeptr = [this] {
@@ -94,7 +94,7 @@ struct Jit::Impl {
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         jit_interface->is_executing = true;
         const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ struct Jit::Impl {
     }
 
     void Reset() {
-        DEBUG_ASSERT(!jit_interface->is_executing);
+        ASSERT(!jit_interface->is_executing);
         jit_state = {};
     }
 

src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp

@@ -501,7 +501,7 @@ void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.HostCall(code, nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[0].IsImmediate());
+    ASSERT(args[0].IsImmediate());
     const u32 imm = args[0].GetImmediateU32();
     Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, [&](RegList param) {
         code.mov(param[0], imm);
@@ -513,7 +513,7 @@ void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.HostCall(code, nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
     const u64 pc = args[0].GetImmediateU64();
     const u64 exception = args[1].GetImmediateU64();
     Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {

src/dynarmic/src/dynarmic/backend/x64/a64_interface.cpp

@@ -66,13 +66,13 @@ public:
         , emitter(block_of_code, conf, jit)
         , polyfill_options(GenPolyfillOptions(block_of_code))
     {
-        DEBUG_ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
+        ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
     }
 
     ~Impl() = default;
 
     HaltReason Run() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         is_executing = true;
         // TODO: Check code alignment
@@ -92,7 +92,7 @@ public:
     }
 
     HaltReason Step() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
         is_executing = true;
         const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ public:
     }
 
     void Reset() {
-        DEBUG_ASSERT(!is_executing);
+        ASSERT(!is_executing);
         jit_state = {};
     }
 

src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp

@@ -191,12 +191,12 @@ void BlockOfCode::DisableWriting() {
 }
 
 void BlockOfCode::ClearCache() {
-    DEBUG_ASSERT(prelude_complete);
+    ASSERT(prelude_complete);
     SetCodePtr(code_begin);
 }
 
 size_t BlockOfCode::SpaceRemaining() const {
-    DEBUG_ASSERT(prelude_complete);
+    ASSERT(prelude_complete);
     const u8* current_ptr = getCurr<const u8*>();
     if (current_ptr >= &top_[maxSize_])
         return 0;
@@ -466,7 +466,7 @@ void BlockOfCode::SetCodePtr(CodePtr code_ptr) {
 
 void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) {
     size_t current_size = getCurr<const u8*>() - reinterpret_cast<const u8*>(begin);
-    DEBUG_ASSERT(current_size <= size);
+    ASSERT(current_size <= size);
     nop(size - current_size);
 }
 

src/dynarmic/src/dynarmic/backend/x64/constant_pool.cpp

@@ -28,7 +28,7 @@ Xbyak::Address ConstantPool::GetConstant(BlockOfCode& code, const Xbyak::Address
     const auto constant = ConstantT(lower, upper);
     auto it = constant_info.find(constant);
     if (it == constant_info.end()) {
-        DEBUG_ASSERT(insertion_point < pool.size());
+        ASSERT(insertion_point < pool.size());
         ConstantT& target_constant = pool[insertion_point];
         target_constant = constant;
         it = constant_info.insert({constant, &target_constant}).first;

src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp

@@ -148,7 +148,7 @@ void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc) {
 
 void EmitX64::EmitPushRSB(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[0].IsImmediate());
+    ASSERT(args[0].IsImmediate());
     const u64 unique_hash_of_target = args[0].GetImmediateU64();
 
     ctx.reg_alloc.ScratchGpr(code, HostLoc::RCX);
@@ -288,7 +288,7 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitAddCycles(size_t cycles) {
-    DEBUG_ASSERT(cycles < (std::numeric_limits<s32>::max)());
+    ASSERT(cycles < (std::numeric_limits<s32>::max)());
     code.sub(qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, cycles_remaining)], static_cast<u32>(cycles));
 }
 

src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp

@@ -129,7 +129,7 @@ void EmitX64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitTestBit(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     // TODO: Flag optimization
     code.bt(result, args[1].GetImmediateU8());
     code.setc(result.cvt8());

src/dynarmic/src/dynarmic/backend/x64/emit_x64_floating_point.cpp

@@ -1842,7 +1842,7 @@ void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
     if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
         code.cvtsi2ss(result, from);
     } else {
-        DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
         code.EnterStandardASIMD();
         code.cvtsi2ss(result, from);
         code.LeaveStandardASIMD();
@@ -1878,7 +1878,7 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
     if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
         op();
     } else {
-        DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
         code.EnterStandardASIMD();
         op();
         code.LeaveStandardASIMD();
@@ -1984,7 +1984,7 @@ void EmitX64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());
+    ASSERT(rounding_mode == ctx.FPCR().RMode());
 
     code.cvtsi2sd(result, from);
 
@@ -2003,7 +2003,7 @@ void EmitX64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());
+    ASSERT(rounding_mode == ctx.FPCR().RMode());
 
     code.cvtsi2ss(result, from);
 
@@ -2022,7 +2022,7 @@ void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());
+    ASSERT(rounding_mode == ctx.FPCR().RMode());
 
     if (code.HasHostFeature(HostFeature::AVX512F)) {
         code.vcvtusi2sd(result, result, from);
@@ -2053,7 +2053,7 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
     const size_t fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());
+    ASSERT(rounding_mode == ctx.FPCR().RMode());
 
     if (code.HasHostFeature(HostFeature::AVX512F)) {
         const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(code, args[0]);

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc

@@ -1,6 +1,3 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-
 /* This file is part of the dynarmic project.
  * Copyright (c) 2022 MerryMage
  * SPDX-License-Identifier: 0BSD
@@ -116,7 +113,7 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) {
         });
     } else {
         // Use page table
-        DEBUG_ASSERT(conf.page_table);
+        ASSERT(conf.page_table);
         const auto src_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitReadMemoryMov<bitsize>(code, value_idx, src_ptr, ordered);
 
@@ -203,7 +200,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
         });
     } else {
         // Use page table
-        DEBUG_ASSERT(conf.page_table);
+        ASSERT(conf.page_table);
         const auto dest_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitWriteMemoryMov<bitsize>(code, dest_ptr, value_idx, ordered);
 
@@ -219,7 +216,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(conf.global_monitor != nullptr);
+    ASSERT(conf.global_monitor != nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const bool ordered = IsOrdered(args[2].GetImmediateAccType());
 
@@ -270,7 +267,7 @@ void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(conf.global_monitor != nullptr);
+    ASSERT(conf.global_monitor != nullptr);
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const bool ordered = IsOrdered(args[3].GetImmediateAccType());
 
@@ -323,7 +320,7 @@ void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    ASSERT(conf.global_monitor && conf.fastmem_pointer);
     if (!exception_handler.SupportsFastmem()) {
         EmitExclusiveReadMemory<bitsize, callback>(ctx, inst);
         return;
@@ -400,7 +397,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in
 
 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    ASSERT(conf.global_monitor && conf.fastmem_pointer);
     if (!exception_handler.SupportsFastmem()) {
         EmitExclusiveWriteMemory<bitsize, callback>(ctx, inst);
         return;

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h

@@ -148,7 +148,7 @@ template<>
             code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
         }
     } else {
-        DEBUG_ASSERT(valid_page_index_bits < 32);
+        ASSERT(valid_page_index_bits < 32);
         code.mov(tmp, vaddr);
         code.shr(tmp, int(page_table_const_bits));
         code.test(tmp, u32(-(1 << valid_page_index_bits)));

src/dynarmic/src/dynarmic/backend/x64/emit_x64_saturation.cpp

@@ -118,7 +118,7 @@ void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const size_t N = args[1].GetImmediateU8();
-    DEBUG_ASSERT(N >= 1 && N <= 32);
+    ASSERT(N >= 1 && N <= 32);
 
     if (N == 32) {
         if (overflow_inst) {
@@ -167,7 +167,7 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) {
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     const size_t N = args[1].GetImmediateU8();
-    DEBUG_ASSERT(N <= 31);
+    ASSERT(N <= 31);
 
     const u32 saturated_value = (1u << N) - 1;
 

src/dynarmic/src/dynarmic/backend/x64/emit_x64_sha.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -18,7 +18,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {
 
     const bool part1 = args[3].GetImmediateU1();
 
-    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));
+    ASSERT(code.HasHostFeature(HostFeature::SHA));
 
     //      3   2   1   0
     // x =  d   c   b   a
@@ -54,7 +54,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
-    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));
+    ASSERT(code.HasHostFeature(HostFeature::SHA));
 
     const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
     const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -67,7 +67,7 @@ void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule1(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
-    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));
+    ASSERT(code.HasHostFeature(HostFeature::SHA));
 
     const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
     const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);

src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp

@@ -177,7 +177,7 @@ static void EmitTwoArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Ins
 
 void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -201,7 +201,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -214,7 +214,7 @@ void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     // TODO: DefineValue directly on Argument for index == 0
@@ -235,7 +235,7 @@ void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     if (index == 0) {
@@ -263,7 +263,7 @@ void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -295,7 +295,7 @@ void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
 
     auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
@@ -308,7 +308,7 @@ void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -331,7 +331,7 @@ void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
     auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
@@ -717,9 +717,9 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 16);
+    ASSERT(index < 16);
     if (index > 0) {
         code.psrldq(a, index);
     }
@@ -741,9 +741,9 @@ void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst)
 void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 8);
+    ASSERT(index < 8);
     if (index > 0) {
         code.psrldq(a, u8(index * 2));
     }
@@ -754,9 +754,9 @@ void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 4);
+    ASSERT(index < 4);
 
     if (index > 0) {
         code.psrldq(a, u8(index * 4));
@@ -770,9 +770,9 @@ void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 16);
+    ASSERT(index < 16);
     if (index > 0) {
         code.psrldq(a, index);
     }
@@ -794,9 +794,9 @@ void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 8);
+    ASSERT(index < 8);
     if (index == 0 && code.HasHostFeature(HostFeature::AVX2)) {
         code.vpbroadcastw(a, a);
     } else {
@@ -814,9 +814,9 @@ void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 4);
+    ASSERT(index < 4);
 
     code.pshufd(a, a, mcl::bit::replicate_element<2, u8>(index));
 
@@ -826,9 +826,9 @@ void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement64(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    DEBUG_ASSERT(args[1].IsImmediate());
+    ASSERT(args[1].IsImmediate());
     const u8 index = args[1].GetImmediateU8();
-    DEBUG_ASSERT(index < 2);
+    ASSERT(index < 2);
 
     if (code.HasHostFeature(HostFeature::AVX)) {
         code.vpermilpd(a, a, mcl::bit::replicate_element<1, u8>(index));
@@ -1314,7 +1314,7 @@ void EmitX64::EmitVectorExtract(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
 
     const u8 position = args[2].GetImmediateU8();
-    DEBUG_ASSERT(position % 8 == 0);
+    ASSERT(position % 8 == 0);
 
     if (position == 0) {
         ctx.reg_alloc.DefineValue(code, inst, args[0]);
@@ -1346,7 +1346,7 @@ void EmitX64::EmitVectorExtractLower(EmitContext& ctx, IR::Inst* inst) {
     auto const xmm_a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
 
     const u8 position = args[2].GetImmediateU8();
-    DEBUG_ASSERT(position % 8 == 0);
+    ASSERT(position % 8 == 0);
 
     if (position != 0) {
         auto const xmm_b = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -3821,7 +3821,7 @@ void EmitX64::EmitVectorRotateWholeVectorRight(EmitContext& ctx, IR::Inst* inst)
     auto const operand = ctx.reg_alloc.UseXmm(code, args[0]);
     auto const result = ctx.reg_alloc.ScratchXmm(code);
     const u8 shift_amount = args[1].GetImmediateU8();
-    DEBUG_ASSERT(shift_amount % 32 == 0);
+    ASSERT(shift_amount % 32 == 0);
     const u8 shuffle_imm = std::rotr<u8>(0b11100100, shift_amount / 32 * 2);
 
     code.pshufd(result, operand, shuffle_imm);
@@ -4914,7 +4914,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
         code.punpcklbw(reconstructed, xmm0);
         break;
     case 32:
-        DEBUG_ASSERT(code.HasHostFeature(HostFeature::SSE41));
+        ASSERT(code.HasHostFeature(HostFeature::SSE41));
         code.packusdw(dest, xmm0);  // SSE4.1
         code.movdqa(reconstructed, dest);
         code.punpcklwd(reconstructed, xmm0);
@@ -5276,11 +5276,11 @@ void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorTable(EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    DEBUG_ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -5438,7 +5438,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
             code.pxor(xmm0, xmm0);
             code.punpcklqdq(xmm_table1, xmm0);
         } else {
-            DEBUG_ASSERT(table_size == 4);
+            ASSERT(table_size == 4);
             auto const xmm_table1_upper = ctx.reg_alloc.UseXmm(code, table[3]);
             code.punpcklqdq(xmm_table1, xmm_table1_upper);
             ctx.reg_alloc.Release(xmm_table1_upper);
@@ -5529,7 +5529,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) {
-    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
 
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());

src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp

@@ -676,7 +676,7 @@ void EmitX64::EmitFPVectorFromSignedFixed32(EmitContext& ctx, IR::Inst* inst) {
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         code.cvtdq2ps(xmm, xmm);
@@ -694,7 +694,7 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) {
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {
@@ -745,7 +745,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst)
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_Ortho)) {
@@ -795,7 +795,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst)
     const int fbits = args[1].GetImmediateU8();
     const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
     const bool fpcr_controlled = args[3].GetImmediateU1();
-    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
 
     MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
         if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {

src/dynarmic/src/dynarmic/backend/x64/exception_handler_windows.cpp

@@ -104,7 +104,7 @@ static PrologueInformation GetPrologueInformation() {
         entry.code.OpInfo = reg;
     };
     const auto alloc_large = [&](u8 offset, size_t size) {
-        DEBUG_ASSERT(size % 8 == 0);
+        ASSERT(size % 8 == 0);
         size /= 8;
 
         auto& entry = next_entry();
@@ -123,7 +123,7 @@ static PrologueInformation GetPrologueInformation() {
         }
     };
     const auto save_xmm128 = [&](u8 offset, u8 reg, size_t frame_offset) {
-        DEBUG_ASSERT(frame_offset % 16 == 0);
+        ASSERT(frame_offset % 16 == 0);
 
         auto& entry = next_entry();
         entry.code.CodeOffset = offset;
@@ -165,7 +165,7 @@ static PrologueInformation GetPrologueInformation() {
         auto& last_entry = next_entry();
         last_entry.FrameOffset = 0;
     }
-    DEBUG_ASSERT(ret.unwind_code.size() % 2 == 0);
+    ASSERT(ret.unwind_code.size() % 2 == 0);
 
     return ret;
 }

src/dynarmic/src/dynarmic/backend/x64/hostloc.h

@@ -78,12 +78,12 @@ constexpr bool HostLocIsFlag(HostLoc reg) {
 }
 
 constexpr HostLoc HostLocRegIdx(int idx) {
-    DEBUG_ASSERT(idx >= 0 && idx <= 15);
+    ASSERT(idx >= 0 && idx <= 15);
     return HostLoc(idx);
 }
 
 constexpr HostLoc HostLocXmmIdx(int idx) {
-    DEBUG_ASSERT(idx >= 0 && idx <= 15);
+    ASSERT(idx >= 0 && idx <= 15);
     return HostLoc(size_t(HostLoc::XMM0) + idx);
 }
 
@@ -159,12 +159,12 @@ const std::bitset<32> any_xmm = BuildRegSet({
 });
 
 inline Xbyak::Reg64 HostLocToReg64(HostLoc loc) noexcept {
-    DEBUG_ASSERT(HostLocIsGPR(loc));
+    ASSERT(HostLocIsGPR(loc));
     return Xbyak::Reg64(int(loc));
 }
 
 inline Xbyak::Xmm HostLocToXmm(HostLoc loc) noexcept {
-    DEBUG_ASSERT(HostLocIsXMM(loc));
+    ASSERT(HostLocIsXMM(loc));
     return Xbyak::Xmm(int(loc) - int(HostLoc::XMM0));
 }
 

src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp

@@ -56,11 +56,11 @@ static inline bool IsValuelessType(const IR::Type type) noexcept {
 }
 
 void HostLocInfo::ReleaseOne() noexcept {
-    DEBUG_ASSERT(is_being_used_count > 0);
+    ASSERT(is_being_used_count > 0);
     --is_being_used_count;
     is_scratch = false;
     if (current_references > 0) {
-        DEBUG_ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+        ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
         ++accumulated_uses;
         --current_references;
         if (current_references == 0)
@@ -69,7 +69,7 @@ void HostLocInfo::ReleaseOne() noexcept {
 }
 
 void HostLocInfo::ReleaseAll() noexcept {
-    DEBUG_ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+    ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
     accumulated_uses += current_references;
     current_references = 0;
     is_set_last_use = false;
@@ -91,7 +91,7 @@ void HostLocInfo::AddValue(HostLoc loc, IR::Inst* inst) noexcept {
     }
     values.push_back(inst);
 
-    DEBUG_ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
+    ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
     total_uses += inst->UseCount();
     max_bit_width = std::max<uint8_t>(max_bit_width, std::countr_zero(GetBitWidth(inst->GetType())));
 }
@@ -129,24 +129,24 @@ bool Argument::GetImmediateU1() const noexcept {
 
 u8 Argument::GetImmediateU8() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
+    ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
     return u8(imm);
 }
 
 u16 Argument::GetImmediateU16() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
+    ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
     return u16(imm);
 }
 
 u32 Argument::GetImmediateU32() const noexcept {
     const u64 imm = value.GetImmediateAsU64();
-    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
+    ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
     return u32(imm);
 }
 
 u64 Argument::GetImmediateS32() const noexcept {
-    DEBUG_ASSERT(FitsInImmediateS32());
+    ASSERT(FitsInImmediateS32());
     return value.GetImmediateAsU64();
 }
 
@@ -155,12 +155,12 @@ u64 Argument::GetImmediateU64() const noexcept {
 }
 
 IR::Cond Argument::GetImmediateCond() const noexcept {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
     return value.GetCond();
 }
 
 IR::AccType Argument::GetImmediateAccType() const noexcept {
-    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
     return value.GetAccType();
 }
 
@@ -201,7 +201,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
             auto const loc = ValueLocation(arg.GetInst());
-            DEBUG_ASSERT(loc && "argument must already been defined");
+            ASSERT(loc && "argument must already been defined");
             LocInfo(*loc).AddArgReference();
         }
     }
@@ -209,7 +209,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
 }
 
 void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
-    DEBUG_ASSERT(IsValueLive(inst) || !inst->HasUses());
+    ASSERT(IsValueLive(inst) || !inst->HasUses());
     for (size_t i = 0; i < inst->NumArgs(); i++) {
         auto const arg = inst->GetArg(i);
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
@@ -222,37 +222,37 @@ void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
 }
 
 Xbyak::Reg64 RegAlloc::UseScratchGpr(BlockOfCode& code, Argument& arg) noexcept {
-    DEBUG_ASSERT(!arg.allocated);
+    ASSERT(!arg.allocated);
     arg.allocated = true;
     return HostLocToReg64(UseScratchImpl(code, arg.value, gpr_order));
 }
 
 Xbyak::Xmm RegAlloc::UseScratchXmm(BlockOfCode& code, Argument& arg) noexcept {
-    DEBUG_ASSERT(!arg.allocated);
+    ASSERT(!arg.allocated);
     arg.allocated = true;
     return HostLocToXmm(UseScratchImpl(code, arg.value, xmm_order));
 }
 
 void RegAlloc::UseScratch(BlockOfCode& code, Argument& arg, HostLoc host_loc) noexcept {
-    DEBUG_ASSERT(!arg.allocated);
+    ASSERT(!arg.allocated);
     arg.allocated = true;
     UseScratchImpl(code, arg.value, BuildRegSet({host_loc}));
 }
 
 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, const Xbyak::Reg& reg) noexcept {
-    DEBUG_ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
     const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
     DefineValueImpl(code, inst, hostloc);
 }
 
 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, Argument& arg) noexcept {
-    DEBUG_ASSERT(!arg.allocated);
+    ASSERT(!arg.allocated);
     arg.allocated = true;
     DefineValueImpl(code, inst, arg.value);
 }
 
 void RegAlloc::Release(const Xbyak::Reg& reg) noexcept {
-    DEBUG_ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
     const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
     LocInfo(hostloc).ReleaseOne();
 }
@@ -382,15 +382,15 @@ void RegAlloc::HostCall(
 }
 
 void RegAlloc::AllocStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    DEBUG_ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    DEBUG_ASSERT(reserved_stack_space == 0);
+    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    ASSERT(reserved_stack_space == 0);
     reserved_stack_space = stack_space;
     code.sub(code.rsp, u32(stack_space));
 }
 
 void RegAlloc::ReleaseStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    DEBUG_ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    DEBUG_ASSERT(reserved_stack_space == stack_space);
+    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    ASSERT(reserved_stack_space == stack_space);
     reserved_stack_space = 0;
     code.add(code.rsp, u32(stack_space));
 }
@@ -449,7 +449,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc
     auto const it_final = it_empty_candidate != HostLoc::FirstSpill
         ? it_empty_candidate : it_candidate != HostLoc::FirstSpill
         ? it_candidate : it_rex_candidate;
-    DEBUG_ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
+    ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
     // Evil magic - increment LRU counter (will wrap at 256)
     const_cast<RegAlloc*>(this)->LocInfo(HostLoc(it_final)).lru_counter++;
     return HostLoc(it_final);
@@ -459,26 +459,26 @@ std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const noex
     for (size_t i = 0; i < hostloc_info.size(); i++)
         if (hostloc_info[i].ContainsValue(value)) {
             //for (size_t j = 0; j < hostloc_info.size(); ++j)
-            //    DEBUG_ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
+            //    ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
             return HostLoc(i);
         }
     return std::nullopt;
 }
 
 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, HostLoc host_loc) noexcept {
-    DEBUG_ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
     LocInfo(host_loc).AddValue(host_loc, def_inst);
-    DEBUG_ASSERT(*ValueLocation(def_inst) == host_loc);
+    ASSERT(*ValueLocation(def_inst) == host_loc);
 }
 
 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::Value& use_inst) noexcept {
-    DEBUG_ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
     if (use_inst.IsImmediate()) {
         const HostLoc location = ScratchImpl(code, gpr_order);
         DefineValueImpl(code, def_inst, location);
         LoadImmediate(code, use_inst, location);
     } else {
-        DEBUG_ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
+        ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
         const HostLoc location = *ValueLocation(use_inst.GetInst());
         DefineValueImpl(code, def_inst, location);
     }
@@ -486,22 +486,22 @@ void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::
 
 void RegAlloc::Move(BlockOfCode& code, HostLoc to, HostLoc from) noexcept {
     const size_t bit_width = LocInfo(from).GetMaxBitWidth();
-    DEBUG_ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
-    DEBUG_ASSERT(bit_width <= HostLocBitWidth(to));
-    DEBUG_ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
+    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
+    ASSERT(bit_width <= HostLocBitWidth(to));
+    ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
     EmitMove(code, bit_width, to, from);
     LocInfo(to) = std::exchange(LocInfo(from), {});
 }
 
 void RegAlloc::CopyToScratch(BlockOfCode& code, size_t bit_width, HostLoc to, HostLoc from) noexcept {
-    DEBUG_ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
+    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
     EmitMove(code, bit_width, to, from);
 }
 
 void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
-    DEBUG_ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
-    DEBUG_ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
-    DEBUG_ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
+    ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
+    ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
+    ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
 
     if (LocInfo(a).IsEmpty()) {
         Move(code, a, b);
@@ -514,16 +514,16 @@ void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
 }
 
 void RegAlloc::MoveOutOfTheWay(BlockOfCode& code, HostLoc reg) noexcept {
-    DEBUG_ASSERT(!LocInfo(reg).IsLocked());
+    ASSERT(!LocInfo(reg).IsLocked());
     if (!LocInfo(reg).IsEmpty()) {
         SpillRegister(code, reg);
     }
 }
 
 void RegAlloc::SpillRegister(BlockOfCode& code, HostLoc loc) noexcept {
-    DEBUG_ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
-    DEBUG_ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
-    DEBUG_ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
+    ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
+    ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
+    ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
     auto const new_loc = FindFreeSpill(HostLocIsXMM(loc));
     Move(code, new_loc, loc);
 }
@@ -559,7 +559,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
     }()
 
 HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_loc) noexcept {
-    DEBUG_ASSERT(imm.IsImmediate() && "imm is not an immediate");
+    ASSERT(imm.IsImmediate() && "imm is not an immediate");
     if (HostLocIsGPR(host_loc)) {
         const Xbyak::Reg64 reg = HostLocToReg64(host_loc);
         const u64 imm_value = imm.GetImmediateAsU64();
@@ -584,9 +584,9 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l
 
 void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc to, const HostLoc from) noexcept {
     auto const spill_to_op_arg_helper = [&](HostLoc loc, size_t reserved_stack_space) {
-        DEBUG_ASSERT(HostLocIsSpill(loc));
+        ASSERT(HostLocIsSpill(loc));
         size_t i = size_t(loc) - size_t(HostLoc::FirstSpill);
-        DEBUG_ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
+        ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
         return Xbyak::util::rsp + reserved_stack_space + ABI_SHADOW_SPACE + offsetof(StackLayout, spill) + i * sizeof(StackLayout::spill[0]);
     };
     auto const spill_xmm_to_op = [&](const HostLoc loc) {
@@ -595,21 +595,21 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
     if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
         MAYBE_AVX(movaps, HostLocToXmm(to), HostLocToXmm(from));
     } else if (HostLocIsGPR(to) && HostLocIsGPR(from)) {
-        DEBUG_ASSERT(bit_width != 128);
+        ASSERT(bit_width != 128);
         if (bit_width == 64) {
             code.mov(HostLocToReg64(to), HostLocToReg64(from));
         } else {
             code.mov(HostLocToReg64(to).cvt32(), HostLocToReg64(from).cvt32());
         }
     } else if (HostLocIsXMM(to) && HostLocIsGPR(from)) {
-        DEBUG_ASSERT(bit_width != 128);
+        ASSERT(bit_width != 128);
         if (bit_width == 64) {
             MAYBE_AVX(movq, HostLocToXmm(to), HostLocToReg64(from));
         } else {
             MAYBE_AVX(movd, HostLocToXmm(to), HostLocToReg64(from).cvt32());
         }
     } else if (HostLocIsGPR(to) && HostLocIsXMM(from)) {
-        DEBUG_ASSERT(bit_width != 128);
+        ASSERT(bit_width != 128);
         if (bit_width == 64) {
             MAYBE_AVX(movq, HostLocToReg64(to), HostLocToXmm(from));
         } else {
@@ -617,7 +617,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
         }
     } else if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
         const Xbyak::Address spill_addr = spill_xmm_to_op(from);
-        DEBUG_ASSERT(spill_addr.getBit() >= bit_width);
+        ASSERT(spill_addr.getBit() >= bit_width);
         switch (bit_width) {
         case 128:
             MAYBE_AVX(movaps, HostLocToXmm(to), spill_addr);
@@ -635,7 +635,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
         }
     } else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
         const Xbyak::Address spill_addr = spill_xmm_to_op(to);
-        DEBUG_ASSERT(spill_addr.getBit() >= bit_width);
+        ASSERT(spill_addr.getBit() >= bit_width);
         switch (bit_width) {
         case 128:
             MAYBE_AVX(movaps, spill_addr, HostLocToXmm(from));
@@ -652,14 +652,14 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
             UNREACHABLE();
         }
     } else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
-        DEBUG_ASSERT(bit_width != 128);
+        ASSERT(bit_width != 128);
         if (bit_width == 64) {
             code.mov(HostLocToReg64(to), Xbyak::util::qword[spill_to_op_arg_helper(from, reserved_stack_space)]);
         } else {
             code.mov(HostLocToReg64(to).cvt32(), Xbyak::util::dword[spill_to_op_arg_helper(from, reserved_stack_space)]);
         }
     } else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
-        DEBUG_ASSERT(bit_width != 128);
+        ASSERT(bit_width != 128);
         if (bit_width == 64) {
             code.mov(Xbyak::util::qword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from));
         } else {
@@ -672,7 +672,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
 #undef MAYBE_AVX
 
 void RegAlloc::EmitExchange(BlockOfCode& code, const HostLoc a, const HostLoc b) noexcept {
-    DEBUG_ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
+    ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
     code.xchg(HostLocToReg64(a), HostLocToReg64(b));
 }
 

src/dynarmic/src/dynarmic/backend/x64/reg_alloc.h

@@ -49,19 +49,19 @@ public:
         return is_being_used_count == 0 && current_references == 1 && size_t(accumulated_uses) + 1 == size_t(total_uses);
     }
     inline void ReadLock() noexcept {
-        DEBUG_ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
-        DEBUG_ASSERT(!bool(is_scratch));
+        ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
+        ASSERT(!bool(is_scratch));
         is_being_used_count++;
     }
     inline void WriteLock() noexcept {
-        DEBUG_ASSERT(is_being_used_count == 0);
+        ASSERT(is_being_used_count == 0);
         is_being_used_count++;
         is_scratch = true;
     }
     inline void AddArgReference() noexcept {
-        DEBUG_ASSERT(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
+        ASSERT(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
         ++current_references;
-        DEBUG_ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses));
+        ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses));
     }
     void ReleaseOne() noexcept;
     void ReleaseAll() noexcept;
@@ -147,12 +147,12 @@ public:
         return !!ValueLocation(inst);
     }
     inline Xbyak::Reg64 UseGpr(BlockOfCode& code, Argument& arg) noexcept {
-        DEBUG_ASSERT(!arg.allocated);
+        ASSERT(!arg.allocated);
         arg.allocated = true;
         return HostLocToReg64(UseImpl(code, arg.value, gpr_order));
     }
     inline Xbyak::Xmm UseXmm(BlockOfCode& code, Argument& arg) noexcept {
-        DEBUG_ASSERT(!arg.allocated);
+        ASSERT(!arg.allocated);
         arg.allocated = true;
         return HostLocToXmm(UseImpl(code, arg.value, xmm_order));
     }
@@ -160,7 +160,7 @@ public:
         return UseGpr(code, arg);
     }
     inline void Use(BlockOfCode& code, Argument& arg, const HostLoc host_loc) noexcept {
-        DEBUG_ASSERT(!arg.allocated);
+        ASSERT(!arg.allocated);
         arg.allocated = true;
         UseImpl(code, arg.value, BuildRegSet({host_loc}));
     }
@@ -205,7 +205,7 @@ public:
             iter.ReleaseAll();
     }
     inline void AssertNoMoreUses() noexcept {
-        DEBUG_ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
+        ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
     }
 #ifndef NDEBUG
     inline void EmitVerboseDebuggingOutput(BlockOfCode& code) noexcept {

src/dynarmic/src/dynarmic/common/fp/fpcr.h

@@ -73,7 +73,7 @@ public:
 
     /// Set rounding mode control field.
     void RMode(FP::RoundingMode rounding_mode) {
-        DEBUG_ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
+        ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
         value = mcl::bit::set_bits<22, 23>(value, static_cast<u32>(rounding_mode));
     }
 
@@ -93,7 +93,7 @@ public:
     /// Set the stride of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Stride(size_t stride) {
-        DEBUG_ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
+        ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
         value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u);
     }
 
@@ -116,7 +116,7 @@ public:
     /// Sets the length of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Len(size_t len) {
-        DEBUG_ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
+        ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
         value = mcl::bit::set_bits<16, 18>(value, static_cast<u32>(len - 1));
     }
 

src/dynarmic/src/dynarmic/common/fp/op/FPRoundInt.cpp

@@ -26,7 +26,7 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) {
-    DEBUG_ASSERT(rounding != RoundingMode::ToOdd);
+    ASSERT(rounding != RoundingMode::ToOdd);
 
     auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);
 

src/dynarmic/src/dynarmic/common/fp/op/FPToFixed.cpp

@@ -25,9 +25,9 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    DEBUG_ASSERT(rounding != RoundingMode::ToOdd);
-    DEBUG_ASSERT(ibits <= 64);
-    DEBUG_ASSERT(fbits <= ibits);
+    ASSERT(rounding != RoundingMode::ToOdd);
+    ASSERT(ibits <= 64);
+    ASSERT(fbits <= ibits);
 
     auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);
 

src/dynarmic/src/dynarmic/common/fp/process_exception.cpp

@@ -18,27 +18,27 @@ namespace Dynarmic::FP {
 void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
     switch (exception) {
     case FPExc::InvalidOp:
-        DEBUG_ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
         fpsr.IOC(true);
         break;
     case FPExc::DivideByZero:
-        DEBUG_ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
         fpsr.DZC(true);
         break;
     case FPExc::Overflow:
-        DEBUG_ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
         fpsr.OFC(true);
         break;
     case FPExc::Underflow:
-        DEBUG_ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
         fpsr.UFC(true);
         break;
     case FPExc::Inexact:
-        DEBUG_ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
         fpsr.IXC(true);
         break;
     case FPExc::InputDenorm:
-        DEBUG_ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
+        ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
         fpsr.IDC(true);
         break;
     default:

src/dynarmic/src/dynarmic/common/fp/process_nan.cpp

@@ -23,7 +23,7 @@ namespace Dynarmic::FP {
 
 template<typename FPT>
 FPT FPProcessNaN(FPType type, FPT op, FPCR fpcr, FPSR& fpsr) {
-    DEBUG_ASSERT(type == FPType::QNaN || type == FPType::SNaN);
+    ASSERT(type == FPType::QNaN || type == FPType::SNaN);
 
     constexpr size_t topfrac = FPInfo<FPT>::explicit_mantissa_width - 1;
 

src/dynarmic/src/dynarmic/common/fp/unpacked.cpp

@@ -85,8 +85,8 @@ std::tuple<bool, int, u64, ResidualError> Normalize(FPUnpacked op, int extra_rig
 
 template<typename FPT>
 FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    DEBUG_ASSERT(op.mantissa != 0);
-    DEBUG_ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero);
+    ASSERT(op.mantissa != 0);
+    ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero);
 
     constexpr int minimum_exp = FPInfo<FPT>::exponent_min;
     constexpr size_t E = FPInfo<FPT>::exponent_width;