2026-09-11 18:51:14

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64_memory.cpp

@@ -11,7 +11,8 @@
 #include <tuple>
 #include <utility>
 
-#include "common/logging.h"
+#include <fmt/format.h>
+#include <fmt/ostream.h>
 #include "dynarmic/mcl/integer_of_size.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
 

src/dynarmic/src/dynarmic/backend/x64/a32_jitstate.cpp

@@ -69,8 +69,8 @@ u32 A32JitState::Cpsr() const {
     cpsr |= mcl::bit::get_bit<1>(upper_location_descriptor) ? 1 << 9 : 0;
     cpsr |= mcl::bit::get_bit<0>(upper_location_descriptor) ? 1 << 5 : 0;
     // IT state
-    cpsr |= static_cast<u32>(upper_location_descriptor & 0b11111100'00000000);
-    cpsr |= static_cast<u32>(upper_location_descriptor & 0b00000011'00000000) << 17;
+    cpsr |= u32(upper_location_descriptor & 0b11111100'00000000);
+    cpsr |= u32(upper_location_descriptor & 0b00000011'00000000) << 17;
     // Other flags
     cpsr |= cpsr_jaifm;
 
@@ -169,39 +169,36 @@ constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
 u32 A32JitState::Fpscr() const {
     DEBUG_ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
 
-    const u32 fpcr_mode = static_cast<u32>(upper_location_descriptor) & FPSCR_MODE_MASK;
+    const u32 fpcr_mode = u32(upper_location_descriptor) & FPSCR_MODE_MASK;
     const u32 mxcsr = guest_MXCSR | asimd_MXCSR;
-
-    u32 FPSCR = fpcr_mode | fpsr_nzcv;
-    FPSCR |= (mxcsr & 0b0000000000001);       // IOC = IE
-    FPSCR |= (mxcsr & 0b0000000111100) >> 1;  // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
-    FPSCR |= fpsr_exc;
-    FPSCR |= fpsr_qc != 0 ? 1 << 27 : 0;
-
-    return FPSCR;
+    u32 fpscr = fpcr_mode | fpsr_nzcv;
+    fpscr |= (mxcsr & 0b0000000000001);       // IOC = IE
+    fpscr |= (mxcsr & 0b0000000111100) >> 1;  // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
+    fpscr |= fpsr_exc;
+    fpscr |= fpsr_qc != 0 ? 1 << 27 : 0;
+    return fpscr;
 }
 
-void A32JitState::SetFpscr(u32 FPSCR) {
+void A32JitState::SetFpscr(u32 value) {
     // Ensure that only upper half of upper_location_descriptor is used for FPSCR bits.
     static_assert((FPSCR_MODE_MASK & 0xFFFF0000) == FPSCR_MODE_MASK);
 
     upper_location_descriptor &= 0x0000FFFF;
-    upper_location_descriptor |= FPSCR & FPSCR_MODE_MASK;
+    upper_location_descriptor |= value & FPSCR_MODE_MASK;
 
-    fpsr_nzcv = FPSCR & FPSCR_NZCV_MASK;
-    fpsr_qc = (FPSCR >> 27) & 1;
+    fpsr_nzcv = value & FPSCR_NZCV_MASK;
+    fpsr_qc = (value >> 27) & 1;
 
     guest_MXCSR = 0x00001f80;
     asimd_MXCSR = 0x00009fc0;
 
     // RMode
-    const std::array<u32, 4> MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000};
-    guest_MXCSR |= MXCSR_RMode[(FPSCR >> 22) & 0x3];
+    guest_MXCSR |= ((0x6000200040000000 >> (((value >> 18) & (0x3 << 4)))) & 0xf000);
 
     // Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
-    fpsr_exc = FPSCR & 0x9F;
+    fpsr_exc = value & 0x9F;
 
-    if (mcl::bit::get_bit<24>(FPSCR)) {
+    if (mcl::bit::get_bit<24>(value)) {
         // VFP Flush to Zero
         guest_MXCSR |= (1 << 15);  // SSE Flush to Zero
         guest_MXCSR |= (1 << 6);   // SSE Denormals are Zero

src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64_memory.cpp

@@ -11,7 +11,8 @@
 #include <tuple>
 #include <utility>
 
-#include "common/logging.h"
+#include <fmt/format.h>
+#include <fmt/ostream.h>
 #include "dynarmic/mcl/integer_of_size.hpp"
 #include "dynarmic/backend/x64/xbyak.h"
 

src/dynarmic/src/dynarmic/backend/x64/a64_jitstate.cpp

@@ -59,16 +59,16 @@ u32 A64JitState::GetFpcr() const {
 
 void A64JitState::SetFpcr(u32 value) {
     fpcr = value & FPCR_MASK;
-
     asimd_MXCSR &= 0x0000003D;
     guest_MXCSR &= 0x0000003D;
     asimd_MXCSR |= 0x00001f80;
     guest_MXCSR |= 0x00001f80;  // Mask all exceptions
-
     // RMode
-    const std::array<u32, 4> MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000};
-    guest_MXCSR |= MXCSR_RMode[(value >> 22) & 0x3];
-
+    // 0 -> 0x0000
+    // 1 -> 0x4000
+    // 2 -> 0x2000
+    // 3 -> 0x6000
+    guest_MXCSR |= ((0x6000200040000000 >> (((value >> 18) & (0x3 << 4)))) & 0xf000);
     if (mcl::bit::get_bit<24>(value)) {
         guest_MXCSR |= (1 << 15);  // SSE Flush to Zero
         guest_MXCSR |= (1 << 6);   // SSE Denormals are Zero

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc

@@ -14,6 +14,10 @@
 #define AxxJitState CONCATENATE_TOKENS(Axx, JitState)
 #define AxxUserConfig Axx::UserConfig
 
+namespace {
+using Vector = std::array<u64, 2>;
+}
+
 std::optional<AxxEmitX64::DoNotFastmemMarker> AxxEmitX64::ShouldFastmem(AxxEmitContext& ctx, IR::Inst* inst) const {
     if (!conf.fastmem_pointer || !exception_handler.SupportsFastmem()) {
         return std::nullopt;
@@ -27,19 +31,22 @@ std::optional<AxxEmitX64::DoNotFastmemMarker> AxxEmitX64::ShouldFastmem(AxxEmitC
 }
 
 FakeCall AxxEmitX64::FastmemCallback(u64 rip_) {
-    if (auto const it = fastmem_patch_info.find(rip_); it != fastmem_patch_info.end()) {
+    const auto iter = fastmem_patch_info.find(rip_);
+    if (iter != fastmem_patch_info.end()) {
         FakeCall result{
-            .call_rip = it->second.callback,
-            .ret_rip = it->second.resume_rip,
+            .call_rip = iter->second.callback,
+            .ret_rip = iter->second.resume_rip,
         };
-        if (it->second.recompile) {
-            const auto marker = it->second.marker;
+        if (iter->second.recompile) {
+            const auto marker = iter->second.marker;
             do_not_fastmem.insert(marker);
             InvalidateBasicBlocks({std::get<0>(marker)});
         }
         return result;
     }
-    UNREACHABLE_MSG("SIGSEGV @ JIT, rip={:#016x}", rip_); //("iter != fastmem_patch_info.end()");
+    fmt::print("dynarmic: Segfault happened within JITted code at rip = {:016x}\n"
+        "Segfault wasn't at a fastmem patch location!\n", rip_);
+    UNREACHABLE(); //("iter != fastmem_patch_info.end()");
 }
 
 template<std::size_t bitsize, auto callback>
@@ -76,17 +83,22 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) {
 
     const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(code, args[1]);
     const int value_idx = bitsize == 128 ? ctx.reg_alloc.ScratchXmm(code).getIdx() : ctx.reg_alloc.ScratchGpr(code).getIdx();
+
     const auto wrapped_fn = read_fallbacks[std::make_tuple(ordered, bitsize, vaddr.getIdx(), value_idx)];
 
     SharedLabel abort = ctx.GenSharedLabel(), end = ctx.GenSharedLabel();
+
     if (fastmem_marker) {
         // Use fastmem
         bool require_abort_handling = false;
         const auto src_ptr = EmitFastmemVAddr(code, ctx, *abort, vaddr, require_abort_handling);
+
         const auto location = EmitReadMemoryMov<bitsize>(code, value_idx, src_ptr, ordered);
+
         ctx.deferred_emits.emplace_back([=, this, &ctx] {
             code.L(*abort);
             code.call(wrapped_fn);
+
             fastmem_patch_info.emplace(
                 std::bit_cast<u64>(location),
                 FastmemPatchInfo{
@@ -95,23 +107,25 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) {
                     *fastmem_marker,
                     conf.recompile_on_fastmem_failure,
                 });
+
             EmitCheckMemoryAbort(ctx, inst, end);
             code.jmp(*end, code.T_NEAR);
         });
-    } else if (conf.page_table) {
+    } else {
         // Use page table
+        ASSERT(conf.page_table);
         const auto src_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitReadMemoryMov<bitsize>(code, value_idx, src_ptr, ordered);
+
         ctx.deferred_emits.emplace_back([=, this, &ctx] {
             code.L(*abort);
             code.call(wrapped_fn);
             EmitCheckMemoryAbort(ctx, inst, end);
             code.jmp(*end, code.T_NEAR);
         });
-    } else {
-        UNREACHABLE();
     }
     code.L(*end);
+
     if constexpr (bitsize == 128) {
         ctx.reg_alloc.DefineValue(code, inst, Xbyak::Xmm{value_idx});
     } else {
@@ -154,16 +168,18 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
 
     const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(code, args[1]);
     const int value_idx = bitsize == 128
-        ? ctx.reg_alloc.UseXmm(code, args[2]).getIdx()
-        : (ordered ? ctx.reg_alloc.UseScratchGpr(code, args[2]).getIdx() : ctx.reg_alloc.UseGpr(code, args[2]).getIdx());
+                            ? ctx.reg_alloc.UseXmm(code, args[2]).getIdx()
+                            : (ordered ? ctx.reg_alloc.UseScratchGpr(code, args[2]).getIdx() : ctx.reg_alloc.UseGpr(code, args[2]).getIdx());
 
     const auto wrapped_fn = write_fallbacks[std::make_tuple(ordered, bitsize, vaddr.getIdx(), value_idx)];
 
     SharedLabel abort = ctx.GenSharedLabel(), end = ctx.GenSharedLabel();
+
     if (fastmem_marker) {
         // Use fastmem
         bool require_abort_handling = false;
         const auto dest_ptr = EmitFastmemVAddr(code, ctx, *abort, vaddr, require_abort_handling);
+
         const auto location = EmitWriteMemoryMov<bitsize>(code, dest_ptr, value_idx, ordered);
 
         ctx.deferred_emits.emplace_back([=, this, &ctx] {
@@ -182,8 +198,9 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
             EmitCheckMemoryAbort(ctx, inst, end);
             code.jmp(*end, code.T_NEAR);
         });
-    } else if (conf.page_table) {
+    } else {
         // Use page table
+        ASSERT(conf.page_table);
         const auto dest_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
         EmitWriteMemoryMov<bitsize>(code, dest_ptr, value_idx, ordered);
 
@@ -193,8 +210,6 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
             EmitCheckMemoryAbort(ctx, inst, end);
             code.jmp(*end, code.T_NEAR);
         });
-    } else {
-        UNREACHABLE();
     }
     code.L(*end);
 }
@@ -234,8 +249,8 @@ void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
         if (ordered) {
             code.mfence();
         }
-        code.CallLambda([](AxxUserConfig& conf, Axx::VAddr vaddr, u128& ret) {
-            ret = conf.global_monitor->ReadAndMark<u128>(conf.processor_id, vaddr, [&]() -> u128 {
+        code.CallLambda([](AxxUserConfig& conf, Axx::VAddr vaddr, Vector& ret) {
+            ret = conf.global_monitor->ReadAndMark<Vector>(conf.processor_id, vaddr, [&]() -> Vector {
                 return (conf.callbacks->*callback)(vaddr);
             });
         });
@@ -286,8 +301,8 @@ void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
         ctx.reg_alloc.AllocStackSpace(code, 16 + ABI_SHADOW_SPACE);
         code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]);
         code.movaps(xword[code.ABI_PARAM3], xmm1);
-        code.CallLambda([](AxxUserConfig& conf, Axx::VAddr vaddr, u128& value) -> u32 {
-            return conf.global_monitor->DoExclusiveOperation<u128>(conf.processor_id, vaddr, [&](u128 expected) -> bool {
+        code.CallLambda([](AxxUserConfig& conf, Axx::VAddr vaddr, Vector& value) -> u32 {
+            return conf.global_monitor->DoExclusiveOperation<Vector>(conf.processor_id, vaddr, [&](Vector expected) -> bool {
                 return (conf.callbacks->*callback)(vaddr, value, expected);
             }) ? 0 : 1;
         });

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h

@@ -135,16 +135,10 @@ template<>
     if (unused_top_bits == 0) {
         code.mov(tmp, vaddr);
         code.shr(tmp, int(page_table_const_bits));
-        if (ctx.conf.page_table_log2_stride > 3) {
-            code.shl(tmp, int(ctx.conf.page_table_log2_stride));
-            code.mov(page, qword[r14 + tmp.cvt64()]);
-        } else {
-            code.mov(page, qword[r14 + tmp.cvt64() * int(1 << ctx.conf.page_table_log2_stride)]);
-        }
     } else if (ctx.conf.silently_mirror_page_table) {
         if (valid_page_index_bits >= 32) {
             if (code.HasHostFeature(HostFeature::BMI2)) {
-                auto const bit_count = ctx.reg_alloc.ScratchGpr(code);
+                const Xbyak::Reg64 bit_count = ctx.reg_alloc.ScratchGpr(code);
                 code.mov(bit_count, unused_top_bits);
                 code.bzhi(tmp, vaddr, bit_count);
                 code.shr(tmp, int(page_table_const_bits));
@@ -159,31 +153,19 @@ template<>
             code.shr(tmp, int(page_table_const_bits));
             code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
         }
-        if (ctx.conf.page_table_log2_stride > 3) {
-            code.shl(tmp, int(ctx.conf.page_table_log2_stride));
-            code.mov(page, qword[r14 + tmp.cvt64()]);
-        } else {
-            code.mov(page, qword[r14 + tmp.cvt64() * int(1 << ctx.conf.page_table_log2_stride)]);
-        }
     } else {
-        // Common VA sizes: 39 - 12 => 27, 42 - 12 => 30
-        // Check if bits outside of VA space are non-zero
         ASSERT(valid_page_index_bits < 32);
         code.mov(tmp, vaddr);
-        if (ctx.conf.check_halt_on_memory_access) {
-            auto const tmp2 = ctx.reg_alloc.ScratchGpr(code);
-            code.mov(tmp2, u64(-(1ull << valid_page_index_bits) << page_table_const_bits));
-            code.test(tmp, tmp2);
-            code.jnz(abort, code.T_NEAR);
-            ctx.reg_alloc.Release(tmp2);
-        }
         code.shr(tmp, int(page_table_const_bits));
-        if (ctx.conf.page_table_log2_stride > 3) {
-            code.shl(tmp, int(ctx.conf.page_table_log2_stride));
-            code.mov(page, qword[r14 + tmp.cvt64()]);
-        } else {
-            code.mov(page, qword[r14 + tmp.cvt64() * int(1 << ctx.conf.page_table_log2_stride)]);
-        }
+        code.test(tmp, u32(-(1 << valid_page_index_bits)));
+        code.jnz(abort, code.T_NEAR);
+    }
+
+    if (ctx.conf.page_table_log2_stride > 3) {
+        code.shl(tmp, int(ctx.conf.page_table_log2_stride));
+        code.mov(page, qword[r14 + tmp.cvt64()]);
+    } else {
+        code.mov(page, qword[r14 + tmp.cvt64() * int(1 << ctx.conf.page_table_log2_stride)]);
     }
 
     // check for marked bit, use as unmapped if marked
@@ -211,7 +193,7 @@ template<>
         return page + vaddr;
     }
     code.mov(tmp, vaddr);
-    code.and_(tmp, u32(page_table_const_mask));
+    code.and_(tmp, static_cast<u32>(page_table_const_mask));
     return page + tmp;
 }