2026-09-11 20:03:41

Signed-off-by: lizzie <lizzie@eden-emu.dev>
2026-09-11 19:36:26
2026-09-12 14:48:49 +00:00 · 2026-09-11 20:03:41 +00:00 · 2026-09-11 19:36:26 +00:00 · 2026-09-11 19:25:01 +00:00
118 changed files with 2124 additions and 1301 deletions
@@ -53,6 +53,7 @@ if (YUZU_STATIC_ROOM)
    # disable e v e r y t h i n g
    set(ENABLE_QT OFF)
    set(YUZU_CMD OFF)
+    set(ENABLE_CUBEB OFF)
    set(ENABLE_UPDATE_CHECKER OFF)
    set(USE_DISCORD_PRESENCE OFF)
    set(BUILD_TESTING OFF)
@@ -216,6 +217,8 @@ if(MSVC)
 endif()

 # TODO(crueter): Cleanup, each dep that has a bundled option should allow to choose between bundled, external, system
+option(ENABLE_CUBEB "Enables the cubeb audio backend" ON)
+
 set(EXT_DEFAULT OFF)
 if (MSVC OR ANDROID)
    set(EXT_DEFAULT ON)
@@ -574,6 +577,10 @@ if (NOT YUZU_STATIC_ROOM)
        find_package(DiscordRPC)
    endif()

+    if (ENABLE_CUBEB)
+        find_package(cubeb)
+    endif()
+
    if (YUZU_TESTS OR DYNARMIC_TESTS)
        find_package(Catch2)
    endif()
@@ -46,6 +46,18 @@
        "repo": "arun11299/cpp-jwt",
        "version": "7f24eb4c32"
    },
+    "cubeb": {
+        "find_args": "CONFIG",
+        "hash": "8a4bcb2f83ba590f52c66626e895304a73eb61928dbc57777e1822e55378e3568366f17f9da4b80036cc2ef4ea9723c32abf6e7d9bbe00fb03654f0991596ab0",
+        "options": [
+            "USE_SANITIZERS OFF",
+            "BUILD_TESTS OFF",
+            "BUILD_TOOLS OFF",
+            "BUNDLE_SPEEX ON"
+        ],
+        "repo": "mozilla/cubeb",
+        "version": "fa02160712"
+    },
    "discord-rpc": {
        "find_args": "MODULE",
        "hash": "8d680b3a16d6f6bf292ad823cf8635595ff986f2a49f758e3009f505b540a9d75194a8cf44cddea75736a8c3e3b5160166e716a0939ce3f18cc463cf648753fe",
@@ -100,6 +100,8 @@ For reasons unberknownst to any human being, `glslangValidator` will crash upon

 For this reason this patch is NOT applied to default on all platforms (for obvious reasons) - instead this is a HaikuOS specific patch, apply with `git apply <absolute path to patch>` after cloning SPIRV-Tools then `make -C build` and add the resulting binary (in `build/StandAlone/glslang`) into PATH.

+`cubeb_devel` will also not work, either disable cubeb or uninstall it.
+
 Still will not run flawlessly until `mesa-24` is available. Modify CMakeCache.txt with the `.so` of libGL and libGLESv2 by doing the incredibly difficult task of copy pasting them (`cp /boot/system/lib/libGL.so .`)

 If you have `quazip1_qt6_devel`, uninstall it. It may call `Core5Compat` on CMake which is wrongly packaged.
@@ -73,6 +73,7 @@ Certain other dependencies will be fetched by CPM regardless. System packages *c

 * [SimpleIni](https://github.com/brofield/simpleini)
 * [DiscordRPC](https://github.com/eden-emulator/discord-rpc)
+* [cubeb](https://github.com/mozilla/cubeb)
 * [libusb](https://github.com/libusb/libusb)
 * [VulkanMemoryAllocator](https://github.com/GPUOpen-LibrariesAndSDKs/VulkanMemoryAllocator)
 * [sirit](https://github.com/eden-emulator/sirit)
@@ -121,7 +122,7 @@ sudo emerge -a \
    dev-util/spirv-tools dev-util/spirv-headers dev-util/vulkan-headers \
    dev-util/vulkan-utility-libraries dev-util/glslang \
    media-gfx/renderdoc media-libs/libva media-libs/opus media-video/ffmpeg \
-    media-libs/VulkanMemoryAllocator media-libs/libsdl3 \
+    media-libs/VulkanMemoryAllocator media-libs/libsdl3 media-libs/cubeb \
    net-libs/enet \
    sys-libs/zlib \
    dev-cpp/nlohmann_json dev-cpp/simpleini dev-cpp/cpp-httplib dev-cpp/cpp-jwt \
@@ -355,7 +356,7 @@ pacman -Syuu --needed --noconfirm $packages
 <summary>HaikuOS</summary>

 ```sh
-pkgman install git cmake patch libfmt_devel nlohmann_json lz4_devel opus_devel boost1.90_devel vulkan_devel qt6_base_devel qt6_declarative_devel libsdl3_devel ffmpeg7_devel libx11_devel enet_devel catch2_devel quazip1_qt5_devel qt6_5compat_devel glslang qt6_devel qt6_charts_devel simpleini quazip_qt6_devel
+pkgman install git cmake patch libfmt_devel nlohmann_json lz4_devel opus_devel boost1.90_devel vulkan_devel qt6_base_devel qt6_declarative_devel libsdl3_devel ffmpeg7_devel libx11_devel enet_devel catch2_devel quazip1_qt5_devel qt6_5compat_devel glslang qt6_devel qt6_charts_devel cubeb_devel simpleini quazip_qt6_devel
 ```

 [Caveats](./Caveats.md#haikuos).
@@ -4,7 +4,7 @@ Modern game consoles require heavy power to be emulated appropriately. This is w

 For example, take a disk write, instead of emulating a proper SD card we instead use the C++ standard library for I/O. Additionally we use the abstractions provided by the `fs` service to "lie" to programs about certain SD card properties. Notably this includes making up sizes for the fake SD card, giving "realistic" values or expected outputs for a given card, and so on. And instead of writing to an actual SD card, the emulator simply writes to a file.

-This also means grand part of the emulator consists of just re-implementing firmware but using HLE primitives; for example audio doesn't go to an emulated audio device, but rather gets processed on the fly by a dedicated service and then passed to SDL3 or null backend.
+This also means grand part of the emulator consists of just re-implementing firmware but using HLE primitives; for example audio doesn't go to an emulated audio device, but rather gets processed on the fly by a dedicated service and then passed to SDL3/cubeb/etc.

 As such, many of the systems implemented are not 100% accurate to the original software, but they're "good enough" to pass as being so. While we do strive to maintain high compatibility (especially with homebrew), there are realistic limitations to these approaches.

@@ -35,6 +35,8 @@ These options control dependencies.

 - `ENABLE_WEB_SERVICE` (ON) Enable multiplayer service
 - `ENABLE_WIFI_SCAN` (OFF) Enable WiFi scanning (requires iw on Linux) - experimental
+- `ENABLE_CUBEB` (ON) Enables the cubeb audio backend
+  - This option is subject for removal.
 - `YUZU_TESTS` (ON) Compile tests - requires Catch2
 - `ENABLE_LTO` (OFF) Enable link-time optimization
  - Not recommended on Windows
@@ -106,6 +106,36 @@ endif()
 # SimpleIni
 AddJsonPackage(simpleini)

+# Most linux distros don't package cubeb, so enable regardless of cpm settings
+if(ENABLE_CUBEB)
+    AddJsonPackage(cubeb)
+
+    if (cubeb_ADDED)
+        if (NOT MSVC)
+            if (TARGET speex)
+                target_compile_options(speex PRIVATE $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-sign-compare>)
+            endif()
+            set_target_properties(cubeb PROPERTIES COMPILE_OPTIONS "")
+            target_compile_options(cubeb INTERFACE
+                $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-implicit-const-int-float-conversion>
+                $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-shadow>
+                $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-missing-declarations>
+                $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-return-type>
+                $<$<COMPILE_LANGUAGE:C,CXX>:-Wno-uninitialized>
+            )
+        else()
+            target_compile_options(cubeb PRIVATE
+                /wd4456
+                /wd4458
+            )
+        endif()
+    endif()
+
+    if (NOT TARGET cubeb::cubeb)
+        add_library(cubeb::cubeb ALIAS cubeb)
+    endif()
+endif()
+
 if (NOT YUZU_USE_BUNDLED_SDL3)
    if (NOT WIN32)
        # Yuzu itself needs: Atomic Audio Events Joystick Haptic Sensor Threads Timers
@@ -15,7 +15,7 @@ pkgs.mkShellNoCC {
    enet libopus vulkan-headers vulkan-utility-libraries
    spirv-tools spirv-headers vulkan-loader unzip
    glslang python3 httplib cpp-jwt ffmpeg-headless
-    libusb1
+    libusb1 cubeb
    # eden
    qt6.qtbase qt6.qtmultimedia qt6.qtwayland qt6.qttools
    qt6.qtwebengine qt6.qt5compat
@@ -58,6 +58,13 @@ class LicensesFragment : Fragment() {
                R.string.license_fidelityfx_fsr_copyright,
                R.string.license_fidelityfx_fsr_text
            ),
+            License(
+                R.string.license_cubeb,
+                R.string.license_cubeb_description,
+                R.string.license_cubeb_link,
+                R.string.license_cubeb_copyright,
+                R.string.license_cubeb_text
+            ),
            License(
                R.string.license_dynarmic,
                R.string.license_dynarmic_description,
@@ -799,6 +799,9 @@
    <string name="theme_mode_light">روشن</string>
    <string name="theme_mode_dark">تاریک</string>

+    <!-- Audio output engines -->
+    <string name="cubeb">cubeb</string>
+
    <!-- Anisotropic filtering options -->
    <string name="multiplier_x2">x2</string>
    <string name="multiplier_x4">x4</string>
@@ -466,11 +466,13 @@
    <string-array name="outputEngineEntries">
        <item>@string/auto</item>
        <item>@string/sdl3</item>
+        <item>@string/cubeb</item>
        <item>@string/string_null</item>
    </string-array>
    <integer-array name="outputEngineValues">
        <item>0</item>
        <item>2</item>
+        <item>1</item>
        <item>3</item>
    </integer-array>

@@ -1262,6 +1262,7 @@

    <!-- Audio output engines -->
    <string name="sdl3" translatable="false">SDL3</string>
+    <string name="cubeb" translatable="false">cubeb</string>

    <!-- Anisotropic filtering options -->
    <string name="multiplier_x2" translatable="false">x2</string>
@@ -1401,6 +1402,23 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 THE SOFTWARE.
+    </string>
+    <string name="license_cubeb" translatable="false">cubeb</string>
+    <string name="license_cubeb_description" translatable="false">Cross platform audio library</string>
+    <string name="license_cubeb_link" translatable="false">https://github.com/mozilla/cubeb</string>
+    <string name="license_cubeb_copyright" translatable="false">Copyright © 2011 Mozilla Foundation</string>
+    <string name="license_cubeb_text" translatable="false">
+Permission to use, copy, modify, and distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.\n\n
+
+THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
    </string>
    <string name="license_dynarmic" translatable="false">Dynarmic</string>
    <string name="license_dynarmic_description" translatable="false">An ARM dynamic recompiler</string>
@@ -229,6 +229,15 @@ endif()
 target_include_directories(audio_core PRIVATE ${OPUS_INCLUDE_DIRS})
 target_link_libraries(audio_core PUBLIC common core Opus::opus)

+if (ENABLE_CUBEB)
+    target_sources(audio_core PRIVATE
+        sink/cubeb_sink.cpp
+        sink/cubeb_sink.h)
+
+    target_link_libraries(audio_core PRIVATE cubeb::cubeb)
+    target_compile_definitions(audio_core PRIVATE HAVE_CUBEB=1)
+endif()
+
 target_sources(audio_core PRIVATE
    sink/sdl3_sink.cpp
    sink/sdl3_sink.h)
@@ -236,8 +245,4 @@ target_sources(audio_core PRIVATE
 target_link_libraries(audio_core PRIVATE SDL3::SDL3)
 target_compile_definitions(audio_core PRIVATE HAVE_SDL3)

-if (ANDROID)
-    target_link_libraries(audio_core PRIVATE OpenSLES)
-endif()
-
 create_target_directory_groups(audio_core)
@@ -0,0 +1,450 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <span>
+#include <vector>
+
+#include "audio_core/common/common.h"
+#include "audio_core/sink/cubeb_sink.h"
+#include "audio_core/sink/sink_stream.h"
+#include "common/logging.h"
+#include "common/scope_exit.h"
+#include "core/core.h"
+
+#ifdef _WIN32
+#include <objbase.h>
+#undef CreateEvent
+#endif
+
+namespace AudioCore::Sink {
+/**
+ * Cubeb sink stream, responsible for sinking samples to hardware.
+ */
+class CubebSinkStream final : public SinkStream {
+public:
+    /**
+     * Create a new sink stream.
+     *
+     * @param ctx_             - Cubeb context to create this stream with.
+     * @param device_channels_ - Number of channels supported by the hardware.
+     * @param system_channels_ - Number of channels the audio systems expect.
+     * @param output_device    - Cubeb output device id.
+     * @param input_device     - Cubeb input device id.
+     * @param name_            - Name of this stream.
+     * @param type_            - Type of this stream.
+     * @param system_          - Core system.
+     * @param event            - Event used only for audio renderer, signalled on buffer consume.
+     */
+    CubebSinkStream(cubeb* ctx_, u32 device_channels_, u32 system_channels_,
+                    cubeb_devid output_device, cubeb_devid input_device, const std::string& name_,
+                    StreamType type_, Core::System& system_)
+        : SinkStream(system_, type_), ctx{ctx_} {
+#ifdef _WIN32
+        CoInitializeEx(nullptr, COINIT_MULTITHREADED);
+#endif
+        name = name_;
+        device_channels = device_channels_;
+        system_channels = system_channels_;
+
+        cubeb_stream_params params{};
+        params.rate = TargetSampleRate;
+        params.channels = device_channels;
+        params.format = CUBEB_SAMPLE_S16LE;
+        params.prefs = CUBEB_STREAM_PREF_NONE;
+        switch (params.channels) {
+        case 1:
+            params.layout = CUBEB_LAYOUT_MONO;
+            break;
+        case 2:
+            params.layout = CUBEB_LAYOUT_STEREO;
+            break;
+        case 6:
+            params.layout = CUBEB_LAYOUT_3F2_LFE;
+            break;
+        }
+
+        u32 minimum_latency{0};
+        const auto latency_error = cubeb_get_min_latency(ctx, &params, &minimum_latency);
+        if (latency_error != CUBEB_OK) {
+            LOG_CRITICAL(Audio_Sink, "Error getting minimum latency, error: {}", latency_error);
+            minimum_latency = TargetSampleCount * 2;
+        }
+
+        minimum_latency = (std::max)(minimum_latency, TargetSampleCount * 2);
+
+        LOG_INFO(Service_Audio,
+                 "Opening cubeb stream {} type {} with: rate {} channels {} (system channels {}) "
+                 "latency {}",
+                 name, type, params.rate, params.channels, system_channels, minimum_latency);
+
+        auto init_error{0};
+        if (type == StreamType::In) {
+            init_error = cubeb_stream_init(ctx, &stream_backend, name.c_str(), input_device,
+                                           &params, output_device, nullptr, minimum_latency,
+                                           &CubebSinkStream::DataCallback,
+                                           &CubebSinkStream::StateCallback, this);
+        } else {
+            init_error = cubeb_stream_init(ctx, &stream_backend, name.c_str(), input_device,
+                                           nullptr, output_device, &params, minimum_latency,
+                                           &CubebSinkStream::DataCallback,
+                                           &CubebSinkStream::StateCallback, this);
+        }
+
+        if (init_error != CUBEB_OK) {
+            LOG_CRITICAL(Audio_Sink, "Error initializing cubeb stream, error: {}", init_error);
+            return;
+        }
+    }
+
+    /**
+     * Destroy the sink stream.
+     */
+    ~CubebSinkStream() override {
+        LOG_DEBUG(Service_Audio, "Destructing cubeb stream {}", name);
+
+        if (!ctx) {
+            return;
+        }
+
+        Finalize();
+
+#ifdef _WIN32
+        CoUninitialize();
+#endif
+    }
+
+    /**
+     * Finalize the sink stream.
+     */
+    void Finalize() override {
+        Stop();
+        cubeb_stream_destroy(stream_backend);
+    }
+
+    /**
+     * Start the sink stream.
+     *
+     * @param resume - Set to true if this is resuming the stream a previously-active stream.
+     *                 Default false.
+     */
+    void Start(bool resume = false) override {
+        if (!ctx || !paused) {
+            return;
+        }
+
+        paused = false;
+        if (cubeb_stream_start(stream_backend) != CUBEB_OK) {
+            LOG_CRITICAL(Audio_Sink, "Error starting cubeb stream");
+        }
+    }
+
+    /**
+     * Stop the sink stream.
+     */
+    void Stop() override {
+        if (!ctx || paused) {
+            return;
+        }
+
+        SignalPause();
+        if (cubeb_stream_stop(stream_backend) != CUBEB_OK) {
+            LOG_CRITICAL(Audio_Sink, "Error stopping cubeb stream");
+        }
+    }
+
+private:
+    /**
+     * Main callback from Cubeb. Either expects samples from us (audio render/audio out), or will
+     * provide samples to be copied (audio in).
+     *
+     * @param stream      - Cubeb-specific data about the stream.
+     * @param user_data   - Custom data pointer passed along, points to a CubebSinkStream.
+     * @param in_buff     - Input buffer to be used if the stream is an input type.
+     * @param out_buff    - Output buffer to be used if the stream is an output type.
+     * @param num_frames_ - Number of frames of audio in the buffers. Note: Not number of samples.
+     */
+    static long DataCallback([[maybe_unused]] cubeb_stream* stream, void* user_data,
+                             [[maybe_unused]] const void* in_buff, void* out_buff,
+                             long num_frames_) {
+        auto* impl = static_cast<CubebSinkStream*>(user_data);
+        if (!impl) {
+            return -1;
+        }
+
+        const std::size_t num_channels = impl->GetDeviceChannels();
+        const std::size_t frame_size = num_channels;
+        const std::size_t num_frames{static_cast<size_t>(num_frames_)};
+
+        if (impl->type == StreamType::In) {
+            std::span<const s16> input_buffer{reinterpret_cast<const s16*>(in_buff),
+                                              num_frames * frame_size};
+            impl->ProcessAudioIn(input_buffer, num_frames);
+        } else {
+            std::span<s16> output_buffer{reinterpret_cast<s16*>(out_buff), num_frames * frame_size};
+            impl->ProcessAudioOutAndRender(output_buffer, num_frames);
+        }
+
+        return num_frames_;
+    }
+
+    /**
+     * Cubeb callback for if a device state changes. Unused currently.
+     *
+     * @param stream      - Cubeb-specific data about the stream.
+     * @param user_data   - Custom data pointer passed along, points to a CubebSinkStream.
+     * @param state       - New state of the device.
+     */
+    static void StateCallback(cubeb_stream*, void*, cubeb_state) {}
+
+    /// Main Cubeb context
+    cubeb* ctx{};
+    /// Cubeb stream backend
+    cubeb_stream* stream_backend{};
+};
+
+CubebSink::CubebSink(std::string_view target_device_name) {
+    // Cubeb requires COM to be initialized on the thread calling cubeb_init on Windows
+#ifdef _WIN32
+    com_init_result = CoInitializeEx(nullptr, COINIT_MULTITHREADED);
+#endif
+
+    if (cubeb_init(&ctx, "Eden", nullptr) != CUBEB_OK) {
+        LOG_CRITICAL(Audio_Sink, "cubeb_init failed");
+        return;
+    }
+
+    if (target_device_name != auto_device_name && !target_device_name.empty()) {
+        cubeb_device_collection collection;
+        if (cubeb_enumerate_devices(ctx, CUBEB_DEVICE_TYPE_OUTPUT, &collection) != CUBEB_OK) {
+            LOG_WARNING(Audio_Sink, "Audio output device enumeration not supported");
+        } else {
+            const auto collection_end{collection.device + collection.count};
+            const auto device{
+                std::find_if(collection.device, collection_end, [&](const cubeb_device_info& info) {
+                    return info.friendly_name != nullptr &&
+                           target_device_name == std::string(info.friendly_name);
+                })};
+            if (device != collection_end) {
+                output_device = device->devid;
+            }
+            cubeb_device_collection_destroy(ctx, &collection);
+        }
+    }
+
+    cubeb_get_max_channel_count(ctx, &device_channels);
+    device_channels = device_channels >= 6U ? 6U : 2U;
+}
+
+CubebSink::~CubebSink() {
+    if (!ctx) {
+        return;
+    }
+
+    for (auto& sink_stream : sink_streams) {
+        sink_stream.reset();
+    }
+
+    cubeb_destroy(ctx);
+
+#ifdef _WIN32
+    if (SUCCEEDED(com_init_result)) {
+        CoUninitialize();
+    }
+#endif
+}
+
+SinkStream* CubebSink::AcquireSinkStream(Core::System& system, u32 system_channels_,
+                                         const std::string& name, StreamType type) {
+    system_channels = system_channels_;
+    SinkStreamPtr& stream = sink_streams.emplace_back(std::make_unique<CubebSinkStream>(
+        ctx, device_channels, system_channels, output_device, input_device, name, type, system));
+
+    return stream.get();
+}
+
+void CubebSink::CloseStream(SinkStream* stream) {
+    for (size_t i = 0; i < sink_streams.size(); i++) {
+        if (sink_streams[i].get() == stream) {
+            sink_streams[i].reset();
+            sink_streams.erase(sink_streams.begin() + i);
+            break;
+        }
+    }
+}
+
+void CubebSink::CloseStreams() {
+    sink_streams.clear();
+}
+
+f32 CubebSink::GetDeviceVolume() const {
+    if (sink_streams.empty()) {
+        return 1.0f;
+    }
+
+    return sink_streams[0]->GetDeviceVolume();
+}
+
+void CubebSink::SetDeviceVolume(f32 volume) {
+    for (auto& stream : sink_streams) {
+        stream->SetDeviceVolume(volume);
+    }
+}
+
+void CubebSink::SetSystemVolume(f32 volume) {
+    for (auto& stream : sink_streams) {
+        stream->SetSystemVolume(volume);
+    }
+}
+
+std::vector<std::string> ListCubebSinkDevices(bool capture) {
+    std::vector<std::string> device_list;
+    cubeb* ctx;
+
+#ifdef _WIN32
+    auto com_init_result = CoInitializeEx(nullptr, COINIT_MULTITHREADED);
+#endif
+
+    if (cubeb_init(&ctx, "Eden Device Enumerator", nullptr) != CUBEB_OK) {
+        LOG_CRITICAL(Audio_Sink, "cubeb_init failed");
+        return {};
+    }
+
+#ifdef _WIN32
+    if (SUCCEEDED(com_init_result)) {
+        CoUninitialize();
+    }
+#endif
+
+    auto type{capture ? CUBEB_DEVICE_TYPE_INPUT : CUBEB_DEVICE_TYPE_OUTPUT};
+    cubeb_device_collection collection;
+    if (cubeb_enumerate_devices(ctx, type, &collection) != CUBEB_OK) {
+        LOG_WARNING(Audio_Sink, "Audio output device enumeration not supported");
+    } else {
+        for (std::size_t i = 0; i < collection.count; i++) {
+            const cubeb_device_info& device = collection.device[i];
+            if (device.friendly_name && device.friendly_name[0] != '\0' &&
+                device.state == CUBEB_DEVICE_STATE_ENABLED) {
+                device_list.emplace_back(device.friendly_name);
+            }
+        }
+        cubeb_device_collection_destroy(ctx, &collection);
+    }
+
+    cubeb_destroy(ctx);
+    return device_list;
+}
+
+/* REVERSION TO 3833 - function GetCubebLatency REINTRODUCED FROM 3833 - DIABLO 3 FIX */
+u32 GetCubebLatency() {
+    cubeb* ctx;
+
+#ifdef _WIN32
+    auto com_init_result = CoInitializeEx(nullptr, COINIT_MULTITHREADED);
+#endif
+
+    // Init cubeb
+    if (cubeb_init(&ctx, "yuzu Latency Getter", nullptr) != CUBEB_OK) {
+        LOG_CRITICAL(Audio_Sink, "cubeb_init failed");
+        // Return a large latency so we choose SDL instead.
+        return 10000u;
+    }
+
+#ifdef _WIN32
+    if (SUCCEEDED(com_init_result)) {
+        CoUninitialize();
+    }
+#endif
+
+    // Get min latency
+    cubeb_stream_params params{};
+    params.rate = TargetSampleRate;
+    params.channels = 2;
+    params.format = CUBEB_SAMPLE_S16LE;
+    params.prefs = CUBEB_STREAM_PREF_NONE;
+    params.layout = CUBEB_LAYOUT_STEREO;
+
+    u32 latency{0};
+    const auto latency_error = cubeb_get_min_latency(ctx, &params, &latency);
+    if (latency_error != CUBEB_OK) {
+        LOG_CRITICAL(Audio_Sink, "Error getting minimum latency, error: {}", latency_error);
+        latency = TargetSampleCount * 2;
+    }
+    latency = (std::max)(latency, TargetSampleCount * 2);
+    cubeb_destroy(ctx);
+    return latency;
+}
+
+// REVERTED back to 3833 - Below namespace section and function IsCubebSuitable() removed, reverting to GetCubebLatency() above. - DIABLO 3 FIX
+/*
+namespace {
+static long TmpDataCallback(cubeb_stream*, void*, const void*, void*, long) {
+    return TargetSampleCount;
+}
+static void TmpStateCallback(cubeb_stream*, void*, cubeb_state) {}
+} // namespace
+
+bool IsCubebSuitable() {
+#if !defined(HAVE_CUBEB)
+    return false;
+#else
+    cubeb* ctx{nullptr};
+
+#ifdef _WIN32
+    auto com_init_result = CoInitializeEx(nullptr, COINIT_MULTITHREADED);
+#endif
+
+    // Init cubeb
+    if (cubeb_init(&ctx, "Eden Latency Getter", nullptr) != CUBEB_OK) {
+        LOG_ERROR(Audio_Sink, "Cubeb failed to init, it is not suitable.");
+        return false;
+    }
+
+    SCOPE_EXIT {
+        cubeb_destroy(ctx);
+    };
+
+#ifdef _WIN32
+    if (SUCCEEDED(com_init_result)) {
+        CoUninitialize();
+    }
+#endif
+
+    // Get min latency
+    cubeb_stream_params params{};
+    params.rate = TargetSampleRate;
+    params.channels = 2;
+    params.format = CUBEB_SAMPLE_S16LE;
+    params.prefs = CUBEB_STREAM_PREF_NONE;
+    params.layout = CUBEB_LAYOUT_STEREO;
+
+    u32 latency{0};
+    const auto latency_error = cubeb_get_min_latency(ctx, &params, &latency);
+    if (latency_error != CUBEB_OK) {
+        LOG_ERROR(Audio_Sink, "Cubeb could not get min latency, it is not suitable.");
+        return false;
+    }
+    latency = (std::max)(latency, TargetSampleCount * 2);
+
+    // Test opening a device with standard parameters
+    cubeb_devid output_device{0};
+    cubeb_devid input_device{0};
+    std::string name{"Eden test"};
+    cubeb_stream* stream{nullptr};
+
+    if (cubeb_stream_init(ctx, &stream, name.c_str(), input_device, nullptr, output_device, &params,
+                          latency, &TmpDataCallback, &TmpStateCallback, nullptr) != CUBEB_OK) {
+        LOG_CRITICAL(Audio_Sink, "Cubeb could not open a device, it is not suitable.");
+        return false;
+    }
+
+    cubeb_stream_stop(stream);
+    cubeb_stream_destroy(stream);
+    return true;
+#endif
+}
+*/
+
+} // namespace AudioCore::Sink
@@ -0,0 +1,118 @@
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include <string>
+#include <vector>
+
+#include <cubeb/cubeb.h>
+
+#include "audio_core/sink/sink.h"
+
+namespace Core {
+class System;
+}
+
+namespace AudioCore::Sink {
+class SinkStream;
+
+/**
+ * Cubeb backend sink, holds multiple output streams and is responsible for sinking samples to
+ * hardware. Used by Audio Render, Audio In and Audio Out.
+ */
+class CubebSink final : public Sink {
+public:
+    explicit CubebSink(std::string_view device_id);
+    ~CubebSink() override;
+
+    /**
+     * Create a new sink stream.
+     *
+     * @param system          - Core system.
+     * @param system_channels - Number of channels the audio system expects.
+     *                          May differ from the device's channel count.
+     * @param name            - Name of this stream.
+     * @param type            - Type of this stream, render/in/out.
+     *
+     * @return A pointer to the created SinkStream
+     */
+    SinkStream* AcquireSinkStream(Core::System& system, u32 system_channels,
+                                  const std::string& name, StreamType type) override;
+
+    /**
+     * Close a given stream.
+     *
+     * @param stream - The stream to close.
+     */
+    void CloseStream(SinkStream* stream) override;
+
+    /**
+     * Close all streams.
+     */
+    void CloseStreams() override;
+
+    /**
+     * Get the device volume. Set from calls to the IAudioDevice service.
+     *
+     * @return Volume of the device.
+     */
+    f32 GetDeviceVolume() const override;
+
+    /**
+     * Set the device volume. Set from calls to the IAudioDevice service.
+     *
+     * @param volume - New volume of the device.
+     */
+    void SetDeviceVolume(f32 volume) override;
+
+    /**
+     * Set the system volume. Comes from the audio system using this stream.
+     *
+     * @param volume - New volume of the system.
+     */
+    void SetSystemVolume(f32 volume) override;
+
+private:
+    /// Backend Cubeb context
+    cubeb* ctx{};
+    /// Cubeb id of the actual hardware output device
+    cubeb_devid output_device{};
+    /// Cubeb id of the actual hardware input device
+    cubeb_devid input_device{};
+    /// Vector of streams managed by this sink
+    std::vector<SinkStreamPtr> sink_streams{};
+
+#ifdef _WIN32
+    /// Cubeb required COM to be initialized multi-threaded on Windows
+    u32 com_init_result = 0;
+#endif
+};
+
+/**
+ * Get a list of connected devices from Cubeb.
+ *
+ * @param capture - Return input (capture) devices if true, otherwise output devices.
+ */
+std::vector<std::string> ListCubebSinkDevices(bool capture);
+
+// REVERSION - function GetCubebLatency() reintroduced from EA-3833 - DIABLO 3 FIX
+/**
+ * Get the reported latency for this sink.
+ *
+ * @return Minimum latency for this sink.
+ */
+u32 GetCubebLatency();
+
+/**
+ * Check if this backend is suitable for use.
+ * Checks if enabled, its latency, whether it opens successfully, etc.
+ *
+ * @return True is this backend is suitable, false otherwise.
+ */
+// bool IsCubebSuitable(); // REVERTED BACK TO GetCubebLatency() FROM 3833
+
+} // namespace AudioCore::Sink
@@ -25,10 +25,9 @@ namespace {
        // See https://github.com/PCSX2/pcsx2/pull/12312
        // "SDL and cubeb backends previously resulted in different names for the output which
        // caused them be identified as different applications by the OS."
+        //
+        // Keep in sync with cubeb_sink.cpp name.
        SDL_SetHint("SDL_AUDIO_DEVICE_APP_NAME", "yuzu Latency Getter");
-        SDL_SetHint("SDL_HINT_AUDIO_DEVICE_STREAM_ROLE", "Game");
-        // We do our own processing, so just have SDL copy our audio
-        SDL_SetHint("SDL_HINT_AUDIO_DEVICE_RAW_STREAM", "1");
 #ifdef __ANDROID__
        SDL_SetHintWithPriority(SDL_HINT_AUDIO_DRIVER, "openslES", SDL_HINT_OVERRIDE);
        if (!SDL_InitSubSystem(SDL_INIT_AUDIO)) {
@@ -91,18 +90,23 @@ public:

        SDL_AudioSpec spec{};
        spec.freq = TargetSampleRate;
-        spec.channels = u8(device_channels);
-        spec.format = SDL_AUDIO_S16LE;
+        spec.channels = static_cast<u8>(device_channels);
+        spec.format = SDL_AUDIO_S16;

-        auto const is_capture = (type == StreamType::In);
-        std::string device_name = is_capture ? input_device : output_device;
-        const SDL_AudioDeviceID audio_device = device_name.empty()
-            ? (is_capture
-                ? SDL_AUDIO_DEVICE_DEFAULT_RECORDING
-                : SDL_AUDIO_DEVICE_DEFAULT_PLAYBACK)
-            : FindAudioDeviceByName(device_name, is_capture);
+        std::string device_name{output_device};
+        bool capture{false};
+        if (type == StreamType::In) {
+            device_name = input_device;
+            capture = true;
+        }

-        stream = SDL_OpenAudioDeviceStream(audio_device, &spec, &SDLSinkStream::DataCallback, this);
+        const SDL_AudioDeviceID audio_device =
+            device_name.empty() ? (capture ? SDL_AUDIO_DEVICE_DEFAULT_RECORDING
+                                           : SDL_AUDIO_DEVICE_DEFAULT_PLAYBACK)
+                                : FindAudioDeviceByName(device_name, capture);
+
+        stream = SDL_OpenAudioDeviceStream(audio_device, &spec, &SDLSinkStream::DataCallback,
+                                           this);

        if (stream == nullptr) {
            LOG_CRITICAL(Audio_Sink, "Error opening SDL audio device: {}", SDL_GetError());
@@ -111,12 +115,13 @@ public:

        SDL_AudioSpec stream_in{};
        SDL_AudioSpec stream_out{};
-        void(SDL_GetAudioStreamFormat(stream, &stream_in, &stream_out));
+        static_cast<void>(SDL_GetAudioStreamFormat(stream, &stream_in, &stream_out));
+
        LOG_INFO(Service_Audio,
                 "Opening SDL stream {} with: rate {} channels {} (system channels {}) "
                 " format {}",
                 static_cast<const void*>(stream), stream_out.freq, stream_out.channels,
-                 system_channels, int(stream_out.format));
+                 system_channels, static_cast<int>(stream_out.format));
    }

    /**
@@ -131,12 +136,14 @@ public:
     * Finalize the sink stream.
     */
    void Finalize() override {
-        if (stream != nullptr) {
-            Stop();
-            SDL_ClearAudioStream(stream);
-            SDL_DestroyAudioStream(stream);
-            stream = nullptr;
+        if (stream == nullptr) {
+            return;
        }
+
+        Stop();
+        SDL_ClearAudioStream(stream);
+        SDL_DestroyAudioStream(stream);
+        stream = nullptr;
    }

    /**
@@ -149,8 +156,9 @@ public:
        if (stream == nullptr || !paused) {
            return;
        }
+
        paused = false;
-        void(SDL_ResumeAudioStreamDevice(stream));
+        static_cast<void>(SDL_ResumeAudioStreamDevice(stream));
    }

    /**
@@ -161,7 +169,7 @@ public:
            return;
        }
        SignalPause();
-        void(SDL_PauseAudioStreamDevice(stream));
+        static_cast<void>(SDL_PauseAudioStreamDevice(stream));
    }

 private:
@@ -173,34 +181,51 @@ private:
     * @param stream   - Buffer of samples to be filled or read.
     * @param len      - Length of the stream in bytes.
     */
-    static void DataCallback(void* userdata, SDL_AudioStream* stream, int additional_amount, int total_amount) {
-        if (auto* impl = static_cast<SDLSinkStream*>(userdata); impl) {
-            auto const num_channels = impl->GetDeviceChannels();
-            auto const frame_size = num_channels;
-            if (impl->type == StreamType::In) {
-                auto const bytes_available = SDL_GetAudioStreamAvailable(stream);
-                if (bytes_available > 0) {
-                    std::vector<s16> input(bytes_available / int(sizeof(s16)));
-                    auto const bytes_read = SDL_GetAudioStreamData(stream, input.data(), bytes_available);
-                    if (bytes_read > 0) {
-                        auto const num_frames = std::size_t(bytes_read) / sizeof(s16) / frame_size;
-                        std::span<const s16> input_buffer{input.data(), std::size_t(bytes_read) / sizeof(s16)};
-                        impl->ProcessAudioIn(input_buffer, num_frames);
-                    }
-                }
-            } else if (additional_amount > 0 || total_amount > 0) {
-                auto const bytes_requested = additional_amount > 0 ? additional_amount : total_amount;
-                std::vector<s16> output(bytes_requested / int(sizeof(s16)));
-                auto const num_frames = std::size_t(bytes_requested) / sizeof(s16) / frame_size;
-                std::span<s16> output_buffer{output.data(), output.size()};
-                impl->ProcessAudioOutAndRender(output_buffer, num_frames);
-                void(SDL_PutAudioStreamData(stream, output.data(), bytes_requested));
+    static void DataCallback(void* userdata, SDL_AudioStream* stream, int additional_amount,
+                             int total_amount) {
+        auto* impl = static_cast<SDLSinkStream*>(userdata);
+
+        if (!impl) {
+            return;
+        }
+
+        const std::size_t num_channels = impl->GetDeviceChannels();
+        const std::size_t frame_size = num_channels;
+
+        if (impl->type == StreamType::In) {
+            const int bytes_available = SDL_GetAudioStreamAvailable(stream);
+            if (bytes_available <= 0) {
+                return;
            }
+
+            std::vector<s16> input(bytes_available / static_cast<int>(sizeof(s16)));
+            const int bytes_read = SDL_GetAudioStreamData(stream, input.data(), bytes_available);
+            if (bytes_read <= 0) {
+                return;
+            }
+
+            const std::size_t num_frames =
+                static_cast<std::size_t>(bytes_read) / sizeof(s16) / frame_size;
+            std::span<const s16> input_buffer{input.data(),
+                                              static_cast<std::size_t>(bytes_read) / sizeof(s16)};
+            impl->ProcessAudioIn(input_buffer, num_frames);
+        } else {
+            if (additional_amount <= 0 && total_amount <= 0) {
+                return;
+            }
+
+            const int bytes_requested = additional_amount > 0 ? additional_amount : total_amount;
+            std::vector<s16> output(bytes_requested / static_cast<int>(sizeof(s16)));
+            const std::size_t num_frames =
+                static_cast<std::size_t>(bytes_requested) / sizeof(s16) / frame_size;
+            std::span<s16> output_buffer{output.data(), output.size()};
+            impl->ProcessAudioOutAndRender(output_buffer, num_frames);
+            static_cast<void>(SDL_PutAudioStreamData(stream, output.data(), bytes_requested));
        }
    }

    /// SDL stream attached to an opened input/output device
-    SDL_AudioStream* stream = nullptr;
+    SDL_AudioStream* stream{};
 };

 SDLSink::SDLSink(std::string_view target_device_name) {
@@ -216,9 +241,11 @@ SDLSink::SDLSink(std::string_view target_device_name) {

 SDLSink::~SDLSink() = default;

-SinkStream* SDLSink::AcquireSinkStream(Core::System& system, u32 system_channels_, const std::string&, StreamType type) {
+SinkStream* SDLSink::AcquireSinkStream(Core::System& system, u32 system_channels_,
+                                       const std::string&, StreamType type) {
    system_channels = system_channels_;
-    SinkStreamPtr& stream = sink_streams.emplace_back(std::make_unique<SDLSinkStream>(device_channels, system_channels, output_device, input_device, type, system));
+    SinkStreamPtr& stream = sink_streams.emplace_back(std::make_unique<SDLSinkStream>(
+        device_channels, system_channels, output_device, input_device, type, system));
    return stream.get();
 }

@@ -237,7 +264,11 @@ void SDLSink::CloseStreams() {
 }

 f32 SDLSink::GetDeviceVolume() const {
-    return sink_streams.empty() ? 1.0f : sink_streams[0]->GetDeviceVolume();
+    if (sink_streams.empty()) {
+        return 1.0f;
+    }
+
+    return sink_streams[0]->GetDeviceVolume();
 }

 void SDLSink::SetDeviceVolume(f32 volume) {
@@ -252,21 +283,68 @@ void SDLSink::SetSystemVolume(f32 volume) {
    }
 }

-std::vector<std::string> ListSDLSinkDevices(bool is_capture) {
-    std::vector<std::string> device_list{};
-    if (InitializeAudio()) {
-        int device_count = 0;
-        SDL_AudioDeviceID* devices = is_capture ? SDL_GetAudioRecordingDevices(&device_count) : SDL_GetAudioPlaybackDevices(&device_count);
-        if (devices != nullptr) {
-            for (int i = 0; i < device_count; ++i) {
-                if (const char* name = SDL_GetAudioDeviceName(devices[i]); name) {
-                    device_list.emplace_back(name);
-                }
-            }
-            SDL_free(devices);
+std::vector<std::string> ListSDLSinkDevices(bool capture) {
+    if (!InitializeAudio())
+        return {}; //no devices
+
+    std::vector<std::string> device_list;
+    int device_count = 0;
+    SDL_AudioDeviceID* devices =
+        capture ? SDL_GetAudioRecordingDevices(&device_count)
+                : SDL_GetAudioPlaybackDevices(&device_count);
+    if (devices == nullptr) {
+        return device_list;
+    }
+
+    for (int i = 0; i < device_count; ++i) {
+        if (const char* name = SDL_GetAudioDeviceName(devices[i])) {
+            device_list.emplace_back(name);
        }
    }
+    SDL_free(devices);
+
    return device_list;
 }

+/* REVERSION to 3833 - function GetSDLLatency() REINTRODUCED FROM 3833 - DIABLO 3 FIX */
+u32 GetSDLLatency() {
+    return TargetSampleCount * 2;
+}
+
+// REVERTED back to 3833 - Below function IsSDLSuitable() removed, reverting to GetSDLLatency() above. - DIABLO 3 FIX
+/*
+bool IsSDLSuitable() {
+#if !defined(HAVE_SDL3)
+    return false;
+#else
+    // Check SDL can init
+    if (!InitializeAudio()!
+        return false;
+
+    // We can set any latency frequency we want with SDL, so no need to check that.
+
+    // Check we can open a device with standard parameters
+    SDL_AudioSpec spec;
+    spec.freq = TargetSampleRate;
+    spec.channels = 2u;
+    spec.format = AUDIO_S16SYS;
+    spec.samples = TargetSampleCount * 2;
+    spec.callback = nullptr;
+    spec.userdata = nullptr;
+
+    SDL_AudioSpec obtained;
+    auto device = SDL_OpenAudioDevice(nullptr, false, &spec, &obtained, false);
+
+    if (device == 0) {
+        LOG_ERROR(Audio_Sink, "SDL failed to open a device, it is not suitable. Error: {}",
+                  SDL_GetError());
+        return false;
+    }
+
+    SDL_CloseAudioDevice(device);
+    return true;
+#endif
+}
+*/
+
 } // namespace AudioCore::Sink
@@ -90,4 +90,20 @@ private:
 */
 std::vector<std::string> ListSDLSinkDevices(bool capture);

+// REVERSION - function GetSDLLatency() reintroduced from EA-3833 - DIABLO 3 FIX
+/**
+ * Get the reported latency for this sink.
+ *
+ * @return Minimum latency for this sink.
+ */
+u32 GetSDLLatency();
+
+/** REVERTED back to 3833 - Below function IsSDLSuitable() removed, reverting to GetSDLLatency() above. - DIABLO 3 FIX
+ * Check if this backend is suitable for use.
+ * Checks if enabled, its latency, whether it opens successfully, etc.
+ *
+ * @return True is this backend is suitable, false otherwise.
+ */
+//bool IsSDLSuitable(); // REVERTED for GetSDLLatency() from EA-3833
+
 } // namespace AudioCore::Sink
@@ -10,6 +10,9 @@
 #include <vector>

 #include "audio_core/sink/sink_details.h"
+#ifdef HAVE_CUBEB
+#include "audio_core/sink/cubeb_sink.h"
+#endif
 #ifdef HAVE_SDL3
 #include "audio_core/sink/sdl3_sink.h"
 #endif
@@ -31,10 +34,24 @@ struct SinkDetails {
    FactoryFn factory;
    /// A method to call to list available devices.
    ListDevicesFn list_devices;
+    /// Method to get the latency of this backend - REINTRODUCED FROM 3833 - DIABLO 3 FIX
+    LatencyFn latency;
+    /// Check whether this backend is suitable to be used.
+    /// SuitableFn is_suitable; // REVERTED FOR LatencyFn latency ABOVE - DIABLO 3 FIX
 };

 // sink_details is ordered in terms of desirability, with the best choice at the top.
-static constexpr SinkDetails sink_details[] = {
+constexpr SinkDetails sink_details[] = {
+#ifdef HAVE_CUBEB
+    SinkDetails{
+        Settings::AudioEngine::Cubeb,
+        [](std::string_view device_id) -> std::unique_ptr<Sink> {
+            return std::make_unique<CubebSink>(device_id);
+        },
+        &ListCubebSinkDevices,
+        &GetCubebLatency,
+    },
+#endif
 #ifdef HAVE_SDL3
    SinkDetails{
        Settings::AudioEngine::Sdl3,
@@ -42,6 +59,7 @@ static constexpr SinkDetails sink_details[] = {
            return std::make_unique<SDLSink>(device_id);
        },
        &ListSDLSinkDevices,
+        &GetSDLLatency,
    },
 #endif
    SinkDetails{
@@ -50,32 +68,69 @@ static constexpr SinkDetails sink_details[] = {
            return std::make_unique<NullSink>(device_id);
        },
        [](bool capture) { return std::vector<std::string>{"null"}; },
+        []() { return 0u; },
    },
 };

 const SinkDetails& GetOutputSinkDetails(Settings::AudioEngine sink_id) {
    const auto find_backend{[](Settings::AudioEngine id) {
-        return std::ranges::find_if(std::begin(sink_details), std::end(sink_details), [&id](const auto& e) {
-            return e.id == id;
-        });
+        return std::find_if(std::begin(sink_details), std::end(sink_details),
+                            [&id](const auto& sink_detail) { return sink_detail.id == id; });
    }};

    auto iter = find_backend(sink_id);
-    if (sink_id == Settings::AudioEngine::Cubeb || sink_id == Settings::AudioEngine::Auto) {
+
+    if (sink_id == Settings::AudioEngine::Auto) {
+        // REVERTED TO 3833 BELOW - DIABLO 3 FIX
+        /*
+        // Auto-select a backend. Use the sink details ordering, preferring cubeb first, checking
+        // that the backend is available and suitable to use.
+        for (auto& details : sink_details) {
+            if (details.is_suitable()) {
+                iter = &details;
+                break;
+            }
+        }
+        */ // END REVERTED CODE - DIABLO 3 FIX
+
+        // BEGIN REINTRODUCED FROM 3833 - REPLACED CODE BLOCK ABOVE - DIABLO 3 FIX
+        // Auto-select a backend. Prefer CubeB, but it may report a large minimum latency which
+        // causes audio issues, in that case go with SDL.
+#if defined(HAVE_CUBEB) && defined(HAVE_SDL3)
+        iter = find_backend(Settings::AudioEngine::Cubeb);
+        if (iter->latency() > TargetSampleCount * 3) {
        iter = find_backend(Settings::AudioEngine::Sdl3);
-        LOG_INFO(Service_Audio, "Auto-selecting the {} backend", Settings::CanonicalizeEnum(iter->id));
+        }
+#else
+        iter = std::begin(sink_details);
+#endif
+        // END REINTRODUCED SECTION FROM 3833 - DIABLO 3 FIX
+        LOG_INFO(Service_Audio, "Auto-selecting the {} backend",
+                 Settings::CanonicalizeEnum(iter->id));
+    /* BEGIN REMOVED - REVERTING BACK TO 3833, this didn't exist at all. - DIABLO 3 FIX
+    } else {
+        if (iter != std::end(sink_details) && !iter->is_suitable()) {
+            LOG_ERROR(Service_Audio, "Selected backend {} is not suitable, falling back to null",
+                      Settings::CanonicalizeEnum(iter->id));
+            iter = find_backend(Settings::AudioEngine::Null);
+        } */ // END REMOVED REVERT - DIABLO 3 FIX
    }
+
    if (iter == std::end(sink_details)) {
        LOG_ERROR(Audio, "Invalid sink_id {}", Settings::CanonicalizeEnum(sink_id));
        iter = find_backend(Settings::AudioEngine::Null);
    }
+
    return *iter;
 }
 } // Anonymous namespace

 std::vector<Settings::AudioEngine> GetSinkIDs() {
    std::vector<Settings::AudioEngine> sink_ids(std::size(sink_details));
-    std::transform(std::begin(sink_details), std::end(sink_details), std::begin(sink_ids), [](const auto& sink) { return sink.id; });
+
+    std::transform(std::begin(sink_details), std::end(sink_details), std::begin(sink_ids),
+                   [](const auto& sink) { return sink.id; });
+
    return sink_ids;
 }

@@ -31,7 +31,7 @@ struct Jit::Impl final {
            , core(conf) {}

    HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));

        jit_interface->is_executing = true;
@@ -42,7 +42,7 @@ struct Jit::Impl final {
    }

    HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));

        jit_interface->is_executing = true;
@@ -31,7 +31,7 @@ struct Jit::Impl final {
            , core(conf) {}

    HaltReason Run() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
        is_executing = true;
        HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
@@ -41,7 +41,7 @@ struct Jit::Impl final {
    }

    HaltReason Step() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&halt_reason)));
        is_executing = true;
        HaltReason hr = core.Step(current_address_space, current_state, &halt_reason);
@@ -57,7 +57,7 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) {
    if (reg.is_vector()) {
        return RegisterList{1} << (reg.index() + 32);
    }
-    ASSERT(reg.index() != 31 && "ZR not allowed in reg list");
+    DEBUG_ASSERT(reg.index() != 31 && "ZR not allowed in reg list");
    if (reg.index() == -1) {
        return RegisterList{1} << 31;
    }
@@ -31,7 +31,7 @@ AddressSpace::AddressSpace(std::size_t code_cache_size)
    , code(mem.ptr(), mem.ptr())
    , fastmem_manager(exception_handler)
 {
-    ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
+    DEBUG_ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");

    exception_handler.Register(mem, code_cache_size);
    exception_handler.SetFastmemCallback([this](u64 host_pc) {
@@ -115,9 +115,13 @@ EmittedBlockInfo AddressSpace::Emit(IR::Block block) {

    EmittedBlockInfo block_info = EmitArm64(code, std::move(block), GetEmitConfig(), fastmem_manager);

-    ASSERT(block_entries.insert({block.Location(), block_info.entry_point}).second);
-    ASSERT(reverse_block_entries.insert({block_info.entry_point, block.Location()}).second);
-    ASSERT(block_infos.insert({block_info.entry_point, block_info}).second);
+    [[maybe_unused]] bool r = true;
+    r &= block_entries.insert({block.Location(), block_info.entry_point}).second;
+    DEBUG_ASSERT(r);
+    r &= reverse_block_entries.insert({block_info.entry_point, block.Location()}).second;
+    DEBUG_ASSERT(r);
+    r &= block_infos.insert({block_info.entry_point, block_info}).second;
+    DEBUG_ASSERT(r);

    Link(block_info);
    RelinkForDescriptor(block.Location(), block_info.entry_point);
@@ -54,7 +54,7 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
    }

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    DEBUG_ASSERT(args[0].IsImmediate());
    const IR::LocationDescriptor target{args[0].GetImmediateU64()};

    code.LDR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr));
@@ -71,19 +71,19 @@ void EmitIR<IR::Opcode::PushRSB>(oaknut::CodeGenerator& code, EmitContext& ctx,
 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }

 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }

 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }

 template<>
@@ -149,13 +149,13 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }

 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.WasValueDefined(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.WasValueDefined(inst));
 }

 template<>
@@ -206,9 +206,9 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
    ebi.entry_point = code.xptr<CodePtr>();

    if (ctx.block.GetCondition() == IR::Cond::AL) {
-        ASSERT(!ctx.block.HasConditionFailedLocation());
+        DEBUG_ASSERT(!ctx.block.HasConditionFailedLocation());
    } else {
-        ASSERT(ctx.block.HasConditionFailedLocation());
+        DEBUG_ASSERT(ctx.block.HasConditionFailedLocation());
        oaknut::Label pass;

        pass = conf.emit_cond(code, ctx, ctx.block.GetCondition());
@@ -234,7 +234,7 @@ void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
    const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);

    auto Sresult = ctx.reg_alloc.WriteS(inst);
@@ -248,7 +248,7 @@ void EmitIR<IR::Opcode::A32GetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));

    if (A32::IsDoubleExtReg(reg)) {
        const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);
@@ -266,7 +266,7 @@ void EmitIR<IR::Opcode::A32GetVector>(oaknut::CodeGenerator& code, EmitContext&
 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
    const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);

    auto Dresult = ctx.reg_alloc.WriteD(inst);
@@ -294,7 +294,7 @@ void EmitIR<IR::Opcode::A32SetRegister>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    DEBUG_ASSERT(A32::IsSingleExtReg(reg));
    const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::S0);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -309,7 +309,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister32>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));
    const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::D0);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -324,7 +324,7 @@ void EmitIR<IR::Opcode::A32SetExtendedRegister64>(oaknut::CodeGenerator& code, E
 template<>
 void EmitIR<IR::Opcode::A32SetVector>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

    if (A32::IsDoubleExtReg(reg)) {
@@ -194,8 +194,8 @@ void EmitIR<IR::Opcode::TestBit>(oaknut::CodeGenerator& code, EmitContext& ctx,
    auto Xresult = ctx.reg_alloc.WriteX(inst);
    auto Xoperand = ctx.reg_alloc.ReadX(args[0]);
    RegAlloc::Realize(Xresult, Xoperand);
-    ASSERT(args[1].IsImmediate());
-    ASSERT(args[1].GetImmediateU8() < 64);
+    DEBUG_ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].GetImmediateU8() < 64);

    code.UBFX(Xresult, Xoperand, args[1].GetImmediateU8(), 1);
 }
@@ -893,9 +893,9 @@ static void EmitAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*

    if (overflow_inst) {
        // There is a limited set of circumstances where this is required, so assert for this.
-        ASSERT(!sub);
-        ASSERT(!nzcv_inst);
-        ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false);
+        DEBUG_ASSERT(!sub);
+        DEBUG_ASSERT(!nzcv_inst);
+        DEBUG_ASSERT(args[2].IsImmediate() && args[2].GetImmediateU1() == false);

        auto Rb = ctx.reg_alloc.ReadReg<bitsize>(args[1]);
        auto Woverflow = ctx.reg_alloc.WriteW(overflow_inst);
@@ -1134,7 +1134,7 @@ static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* i
    if constexpr (!std::is_same_v<EmitFn2, std::nullptr_t>) {
        const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
        const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-        ASSERT(!(nz_inst && nzcv_inst));
+        DEBUG_ASSERT(!(nz_inst && nzcv_inst));
        const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;

        if (flag_inst) {
@@ -1171,7 +1171,7 @@ template<std::size_t bitsize>
 static void EmitAndNot(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
    const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
-    ASSERT(!(nz_inst && nzcv_inst));
+    DEBUG_ASSERT(!(nz_inst && nzcv_inst));
    const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -1402,7 +1402,7 @@ void EmitIR<IR::Opcode::CountLeadingZeros64>(oaknut::CodeGenerator& code, EmitCo
 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[2].IsImmediate());
+    DEBUG_ASSERT(args[2].IsImmediate());

    auto Wresult = ctx.reg_alloc.WriteW(inst);
    auto Wop1 = ctx.reg_alloc.ReadW(args[0]);
@@ -1416,7 +1416,7 @@ void EmitIR<IR::Opcode::ExtractRegister32>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[2].IsImmediate());
+    DEBUG_ASSERT(args[2].IsImmediate());

    auto Xresult = ctx.reg_alloc.WriteX(inst);
    auto Xop1 = ctx.reg_alloc.ReadX(args[0]);
@@ -1430,7 +1430,7 @@ void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());

    auto Wresult = ctx.reg_alloc.WriteW(inst);
    auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
@@ -1444,7 +1444,7 @@ void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext
 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());

    auto Xresult = ctx.reg_alloc.WriteX(inst);
    auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
@@ -68,7 +68,7 @@ static void EmitConvert(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst
    RegAlloc::Realize(Vto, Vfrom);
    ctx.fpsr.Load();

-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());

    emit(Vto, Vfrom);
 }
@@ -106,8 +106,8 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
            }
        }
    } else {
-        ASSERT(fbits == 0);
-        ASSERT(bitsize_to != 16);
+        DEBUG_ASSERT(fbits == 0);
+        DEBUG_ASSERT(bitsize_to != 16);
        if constexpr (is_signed) {
            switch (rounding_mode) {
            case FP::RoundingMode::ToNearest_TieEven:
@@ -449,7 +449,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
    ctx.fpsr.Load();

    if (exact) {
-        ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        DEBUG_ASSERT(ctx.FPCR().RMode() == rounding_mode);
        code.FRINTX(Sresult, Soperand);
    } else {
        switch (rounding_mode) {
@@ -486,7 +486,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
    ctx.fpsr.Load();

    if (exact) {
-        ASSERT(ctx.FPCR().RMode() == rounding_mode);
+        DEBUG_ASSERT(ctx.FPCR().RMode() == rounding_mode);
        code.FRINTX(Dresult, Doperand);
    } else {
        switch (rounding_mode) {
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
 * Copyright (c) 2022 MerryMage
 * SPDX-License-Identifier: 0BSD
@@ -244,7 +247,7 @@ static void EmitPackedAddSub(oaknut::CodeGenerator& code, EmitContext& ctx, IR::
    }

    if (ge_inst) {
-        ASSERT(!is_halving);
+        DEBUG_ASSERT(!is_halving);

        auto Vge = ctx.reg_alloc.WriteD(ge_inst);
        RegAlloc::Realize(Vge);
@@ -24,7 +24,7 @@ using namespace oaknut::util;
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    ASSERT(overflow_inst);
+    DEBUG_ASSERT(overflow_inst);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -44,7 +44,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(oaknut::CodeGenerator& cod
 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
-    ASSERT(overflow_inst);
+    DEBUG_ASSERT(overflow_inst);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto Wresult = ctx.reg_alloc.WriteW(inst);
@@ -67,7 +67,7 @@ void EmitIR<IR::Opcode::SignedSaturation>(oaknut::CodeGenerator& code, EmitConte

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const std::size_t N = args[1].GetImmediateU8();
-    ASSERT(N >= 1 && N <= 32);
+    DEBUG_ASSERT(N >= 1 && N <= 32);

    if (N == 32) {
        ctx.reg_alloc.DefineAsExisting(inst, args[0]);
@@ -113,7 +113,7 @@ void EmitIR<IR::Opcode::UnsignedSaturation>(oaknut::CodeGenerator& code, EmitCon
    ctx.reg_alloc.SpillFlags();

    const std::size_t N = args[1].GetImmediateU8();
-    ASSERT(N <= 31);
+    DEBUG_ASSERT(N <= 31);
    const u32 saturated_value = (1u << N) - 1;

    code.MOV(Wscratch0, saturated_value);
@@ -275,7 +275,7 @@ static void EmitReduce(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst,
 template<std::size_t size, typename EmitFn>
 static void EmitGetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    auto Rresult = ctx.reg_alloc.WriteReg<std::max<std::size_t>(32, size)>(inst);
@@ -310,7 +310,7 @@ void EmitIR<IR::Opcode::VectorGetElement64>(oaknut::CodeGenerator& code, EmitCon
 template<std::size_t size, typename EmitFn>
 static void EmitSetElement(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst, EmitFn emit) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    auto Qvector = ctx.reg_alloc.ReadWriteQ(args[0], inst);
@@ -650,7 +650,7 @@ void EmitIR<IR::Opcode::VectorExtract>(oaknut::CodeGenerator& code, EmitContext&
    auto Qa = ctx.reg_alloc.ReadQ(args[0]);
    auto Qb = ctx.reg_alloc.ReadQ(args[1]);
    const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    DEBUG_ASSERT(position % 8 == 0);
    RegAlloc::Realize(Qresult, Qa, Qb);

    code.EXT(Qresult->B16(), Qa->B16(), Qb->B16(), position / 8);
@@ -663,7 +663,7 @@ void EmitIR<IR::Opcode::VectorExtractLower>(oaknut::CodeGenerator& code, EmitCon
    auto Da = ctx.reg_alloc.ReadD(args[0]);
    auto Db = ctx.reg_alloc.ReadD(args[1]);
    const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    DEBUG_ASSERT(position % 8 == 0);
    RegAlloc::Realize(Dresult, Da, Db);

    code.EXT(Dresult->B8(), Da->B8(), Db->B8(), position / 8);
@@ -958,7 +958,7 @@ void EmitIR<IR::Opcode::VectorMultiply32>(oaknut::CodeGenerator& code, EmitConte

 template<>
 void EmitIR<IR::Opcode::VectorMultiply64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
+    DEBUG_ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
    EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
        code.FMOV(Xscratch0, Qa->toD());
        code.FMOV(Xscratch1, Qb->toD());
@@ -1289,7 +1289,7 @@ void EmitIR<IR::Opcode::VectorReduceAdd64>(oaknut::CodeGenerator& code, EmitCont
 template<>
 void EmitIR<IR::Opcode::VectorRotateWholeVectorRight>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    EmitImmShift<8>(code, ctx, inst, [&](auto Vresult, auto Voperand, u8 shift_amount) {
-        ASSERT(shift_amount % 8 == 0);
+        DEBUG_ASSERT(shift_amount % 8 == 0);
        const u8 ext_imm = (shift_amount % 128) / 8;
        code.EXT(Vresult, Voperand, Voperand, ext_imm);
    });
@@ -1602,12 +1602,12 @@ void EmitIR<IR::Opcode::VectorSub64>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::VectorTable>(oaknut::CodeGenerator&, EmitContext&, IR::Inst* inst) {
    // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    DEBUG_ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }

 template<>
 void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -1674,7 +1674,7 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo

 template<>
 void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -139,7 +139,7 @@ static void EmitFromFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Ins
    const u8 fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
    const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
    RegAlloc::Realize(Qto, Qfrom);

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
@@ -199,7 +199,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                }
            }
        } else {
-            ASSERT(fbits == 0);
+            DEBUG_ASSERT(fbits == 0);
            if constexpr (is_signed) {
                switch (rounding_mode) {
                case FP::RoundingMode::ToNearest_TieEven:
@@ -346,7 +346,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
    const bool fpcr_controlled = args[2].GetImmediateU1();

    auto Qresult = ctx.reg_alloc.WriteQ(inst);
@@ -617,7 +617,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        if (exact) {
-            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            DEBUG_ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
            code.FRINTX(Qresult->S4(), Qoperand->S4());
        } else {
            switch (rounding_mode) {
@@ -657,7 +657,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        if (exact) {
-            ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
+            DEBUG_ASSERT(ctx.FPCR(fpcr_controlled).RMode() == rounding_mode);
            code.FRINTX(Qresult->D2(), Qoperand->D2());
        } else {
            switch (rounding_mode) {
@@ -743,7 +743,7 @@ template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
-    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
    const bool fpcr_controlled = args[2].GetImmediateU1();

    auto Dresult = ctx.reg_alloc.WriteD(inst);
@@ -53,19 +53,19 @@ bool Argument::GetImmediateU1() const {

 u8 Argument::GetImmediateU8() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    DEBUG_ASSERT(imm < 0x100);
    return u8(imm);
 }

 u16 Argument::GetImmediateU16() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    DEBUG_ASSERT(imm < 0x10000);
    return u16(imm);
 }

 u32 Argument::GetImmediateU32() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    DEBUG_ASSERT(imm < 0x100000000);
    return u32(imm);
 }

@@ -74,12 +74,12 @@ u64 Argument::GetImmediateU64() const {
 }

 IR::Cond Argument::GetImmediateCond() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
    return value.GetCond();
 }

 IR::AccType Argument::GetImmediateAccType() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
    return value.GetAccType();
 }

@@ -92,12 +92,12 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }

 void HostLocInfo::SetupScratchLocation() {
-    ASSERT(IsCompletelyEmpty());
+    DEBUG_ASSERT(IsCompletelyEmpty());
    realized = true;
 }

 void HostLocInfo::SetupLocation(const IR::Inst* value) {
-    ASSERT(IsCompletelyEmpty());
+    DEBUG_ASSERT(IsCompletelyEmpty());
    values.clear();
    values.push_back(value);
    realized = true;
@@ -135,7 +135,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
        const IR::Value arg = inst->GetArg(i);
        ret[i].value = arg;
        if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
            ValueInfo(arg.GetInst()).uses_this_inst++;
        }
    }
@@ -174,11 +174,11 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,
    for (int i = 0; i < 4; i++) {
        if (args[i]) {
            if (args[i]->get().GetType() == IR::Type::U128) {
-                ASSERT(fprs[nsrn].IsCompletelyEmpty());
+                DEBUG_ASSERT(fprs[nsrn].IsCompletelyEmpty());
                LoadCopyInto(args[i]->get().value, oaknut::QReg{nsrn});
                nsrn++;
            } else {
-                ASSERT(gprs[ngrn].IsCompletelyEmpty());
+                DEBUG_ASSERT(gprs[ngrn].IsCompletelyEmpty());
                LoadCopyInto(args[i]->get().value, oaknut::XReg{ngrn});
                ngrn++;
            }
@@ -192,7 +192,7 @@ void RegAlloc::PrepareForCall(std::optional<Argument::copyable_reference> arg0,

 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
    defined_insts.insert(inst);
-    ASSERT(!ValueLocation(inst));
+    DEBUG_ASSERT(!ValueLocation(inst));

    if (arg.value.IsImmediate()) {
        inst->ReplaceUsesWith(arg.value);
@@ -206,9 +206,9 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {

 void RegAlloc::DefineAsRegister(IR::Inst* inst, oaknut::Reg reg) {
    defined_insts.insert(inst);
-    ASSERT(!ValueLocation(inst));
+    DEBUG_ASSERT(!ValueLocation(inst));
    auto& info = reg.is_vector() ? fprs[reg.index()] : gprs[reg.index()];
-    ASSERT(info.IsCompletelyEmpty());
+    DEBUG_ASSERT(info.IsCompletelyEmpty());
    info.values.push_back(inst);
    info.expected_uses += inst->UseCount();
 }
@@ -228,18 +228,18 @@ void RegAlloc::UpdateAllUses() {

 void RegAlloc::AssertAllUnlocked() const {
    const auto is_unlocked = [](const auto& i) { return !i.locked && !i.realized; };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
-    ASSERT(is_unlocked(flags));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked));
+    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_unlocked));
+    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_unlocked));
+    DEBUG_ASSERT(is_unlocked(flags));
+    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_unlocked));
 }

 void RegAlloc::AssertNoMoreUses() const {
    const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    ASSERT(is_empty(flags));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    DEBUG_ASSERT(is_empty(flags));
+    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
 }

 void RegAlloc::EmitVerboseDebuggingOutput() {
@@ -271,7 +271,7 @@ void RegAlloc::EmitVerboseDebuggingOutput() {

 template<HostLoc::Kind kind>
 int RegAlloc::GenerateImmediate(const IR::Value& value) {
-    ASSERT(value.GetType() != IR::Type::U1);
+    DEBUG_ASSERT(value.GetType() != IR::Type::U1);
    if constexpr (kind == HostLoc::Kind::Gpr) {
        const int new_location_index = AllocateRegister(gprs, gpr_order);
        SpillGpr(new_location_index);
@@ -309,15 +309,15 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
    }

    const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);

    if (current_location->kind == required_kind) {
        ValueInfo(*current_location).realized = true;
        return current_location->index;
    }

-    ASSERT(!bool(ValueInfo(*current_location).realized));
-    ASSERT(bool(ValueInfo(*current_location).locked));
+    DEBUG_ASSERT(!bool(ValueInfo(*current_location).realized));
+    DEBUG_ASSERT(bool(ValueInfo(*current_location).locked));

    if constexpr (required_kind == HostLoc::Kind::Gpr) {
        const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -328,7 +328,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
            UNREACHABLE(); //logic error
        case HostLoc::Kind::Fpr:
            code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
-            // ASSERT size fits
+            // DEBUG_ASSERT size fits
            break;
        case HostLoc::Kind::Spill:
            code.LDR(oaknut::XReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
@@ -355,7 +355,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
            code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
            break;
        case HostLoc::Kind::Flags:
-            ASSERT(false && "Moving from flags into fprs is not currently supported");
+            DEBUG_ASSERT(false && "Moving from flags into fprs is not currently supported");
            break;
        }

@@ -372,7 +372,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
 template<HostLoc::Kind kind>
 int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
    defined_insts.insert(value);
-    ASSERT(!ValueLocation(value));
+    DEBUG_ASSERT(!ValueLocation(value));

    if constexpr (kind == HostLoc::Kind::Gpr) {
        const int new_location_index = AllocateRegister(gprs, gpr_order);
@@ -407,7 +407,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
        LoadCopyInto(read_value, oaknut::QReg{write_loc});
        return write_loc;
    } else if constexpr (kind == HostLoc::Kind::Flags) {
-        ASSERT(false && "Incorrect function for ReadWrite of flags");
+        DEBUG_ASSERT(false && "Incorrect function for ReadWrite of flags");
    } else {
        UNREACHABLE();
    }
@@ -439,7 +439,7 @@ int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }

 void RegAlloc::SpillGpr(int index) {
-    ASSERT(!gprs[index].locked && !gprs[index].realized);
+    DEBUG_ASSERT(!gprs[index].locked && !gprs[index].realized);
    if (gprs[index].values.empty()) {
        return;
    }
@@ -449,7 +449,7 @@ void RegAlloc::SpillGpr(int index) {
 }

 void RegAlloc::SpillFpr(int index) {
-    ASSERT(!fprs[index].locked && !fprs[index].realized);
+    DEBUG_ASSERT(!fprs[index].locked && !fprs[index].realized);
    if (fprs[index].values.empty()) {
        return;
    }
@@ -461,7 +461,7 @@ void RegAlloc::SpillFpr(int index) {
 void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
    defined_insts.insert(write);
    const auto current_location = ValueLocation(read.value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);

    if (current_location->kind == HostLoc::Kind::Flags) {
        if (!flags.IsOneRemainingUse()) {
@@ -489,7 +489,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
 }

 void RegAlloc::SpillFlags() {
-    ASSERT(!flags.locked && !flags.realized);
+    DEBUG_ASSERT(!flags.locked && !flags.realized);
    if (flags.values.empty()) {
        return;
    }
@@ -501,7 +501,7 @@ void RegAlloc::SpillFlags() {

 int RegAlloc::FindFreeSpill() const {
    const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT(iter != spills.end() && "All spill locations are full");
+    DEBUG_ASSERT(iter != spills.end() && "All spill locations are full");
    return static_cast<int>(iter - spills.begin());
 }

@@ -512,14 +512,14 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::XReg reg) {
    }

    const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);
    switch (current_location->kind) {
    case HostLoc::Kind::Gpr:
        code.MOV(reg, oaknut::XReg{current_location->index});
        break;
    case HostLoc::Kind::Fpr:
        code.FMOV(reg, oaknut::DReg{current_location->index});
-        // ASSERT size fits
+        // DEBUG_ASSERT size fits
        break;
    case HostLoc::Kind::Spill:
        code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
@@ -538,7 +538,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
    }

    const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);
    switch (current_location->kind) {
    case HostLoc::Kind::Gpr:
        code.FMOV(reg.toD(), oaknut::XReg{current_location->index});
@@ -87,7 +87,11 @@ private:
 };

 MachHandler::MachHandler() {
-#define KCHECK(x) ASSERT((x) == KERN_SUCCESS && "init failure at " #x)
+#define KCHECK(x) do { \
+        [[maybe_unused]] auto r = (x); \
+        DEBUG_ASSERT(r == KERN_SUCCESS && "init failure at " #x); \
+    } while (0);
+
    KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port));
    KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND));
    KCHECK(task_set_exception_ports(mach_task_self(), EXC_MASK_BAD_ACCESS, server_port, EXCEPTION_STATE | MACH_EXCEPTION_CODES, THREAD_STATE));
@@ -138,7 +138,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
 #elif defined(ARCHITECTURE_loongarch64)
            CTX_PC = fc.call_pc;
 #else
-            ASSERT(false);
+            DEBUG_ASSERT(false);
 #endif
            return;
        }
@@ -115,7 +115,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
            break;
        }
        default:
-            ASSERT(false && "Invalid relocation target");
+            DEBUG_ASSERT(false && "Invalid relocation target");
        }
    }
 }
@@ -25,7 +25,7 @@ struct Jit::Impl final {
            , current_address_space(conf) {}

    HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        jit_interface->is_executing = true;

        const auto location_descriptor = current_state.GetLocationDescriptor();
@@ -38,7 +38,7 @@ struct Jit::Impl final {
    }

    HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        jit_interface->is_executing = true;

        const auto location_descriptor = A32::LocationDescriptor{current_state.GetLocationDescriptor()}.SetSingleStepping(true);
@@ -20,7 +20,7 @@ public:
    explicit CodeBlock(std::size_t size) noexcept
            : memsize(size) {
        mem = static_cast<u8*>(mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0));
-        ASSERT(mem != MAP_FAILED);
+        DEBUG_ASSERT(mem != MAP_FAILED);
        la_init_assembler(&as, mem, size);
    }

@@ -16,7 +16,7 @@ namespace Dynarmic::Backend::LoongArch64 {

 template<IR::Opcode op>
 void EmitIR(lagoon_assembler_t&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented opcode");
+    DEBUG_ASSERT(false && "Unimplemented opcode");
 }

 template<>
@@ -36,7 +36,7 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t&, EmitContext& ct

 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }

 template<>
@@ -98,7 +98,7 @@ EmittedBlockInfo EmitLoongArch64(lagoon_assembler_t& as, IR::Block block, const
    const auto term = block.GetTerminal();
    const IR::Term::LeafTerminal* leaft_term = std::get_if<IR::Term::LeafTerminal>(&term);
    const IR::Term::LinkBlock* link_block_term = std::get_if<IR::Term::LinkBlock>(leaft_term);
-    ASSERT(link_block_term);
+    DEBUG_ASSERT(link_block_term);
    la_load_immediate64(&as, Xscratch0, link_block_term->next.Value());
    la_st_w(&as, Xscratch0, Xstate, static_cast<int32_t>(offsetof(A32JitState, regs) + sizeof(u32) * 15));

@@ -41,7 +41,7 @@ template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZC>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

-    ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
+    DEBUG_ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());

    auto Xnz = ctx.reg_alloc.ReadX(args[0]);
    auto Xc = ctx.reg_alloc.ReadX(args[1]);
@@ -22,8 +22,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t& as, EmitContext&
    auto& shift_arg = args[1];
    auto& carry_arg = args[2];

-    ASSERT(carry_inst != nullptr);
-    ASSERT(shift_arg.IsImmediate());
+    DEBUG_ASSERT(carry_inst != nullptr);
+    DEBUG_ASSERT(shift_arg.IsImmediate());

    auto Xresult = ctx.reg_alloc.WriteX(inst);
    auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);
@@ -42,19 +42,19 @@ bool Argument::GetImmediateU1() const {

 u8 Argument::GetImmediateU8() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    DEBUG_ASSERT(imm < 0x100);
    return u8(imm);
 }

 u16 Argument::GetImmediateU16() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    DEBUG_ASSERT(imm < 0x10000);
    return u16(imm);
 }

 u32 Argument::GetImmediateU32() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    DEBUG_ASSERT(imm < 0x100000000);
    return u32(imm);
 }

@@ -63,12 +63,12 @@ u64 Argument::GetImmediateU64() const {
 }

 IR::Cond Argument::GetImmediateCond() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
    return value.GetCond();
 }

 IR::AccType Argument::GetImmediateAccType() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
    return value.GetAccType();
 }

@@ -77,7 +77,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }

 void HostLocInfo::SetupScratchLocation() {
-    ASSERT(IsCompletelyEmpty());
+    DEBUG_ASSERT(IsCompletelyEmpty());
    locked = 1;
    realized = true;
 }
@@ -103,7 +103,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
        const IR::Value arg = inst->GetArg(i);
        ret[i].value = arg;
        if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
            ValueInfo(arg.GetInst()).uses_this_inst++;
        }
    }
@@ -121,7 +121,7 @@ void RegAlloc::UpdateAllUses() {
 }

 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
-    ASSERT(!ValueLocation(inst));
+    DEBUG_ASSERT(!ValueLocation(inst));

    if (arg.value.IsImmediate()) {
        inst->ReplaceUsesWith(arg.value);
@@ -136,7 +136,7 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
 void RegAlloc::AssertNoMoreUses() const {
    // TODO: Re-enable this assert once all register allocation issues are fixed
    // const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    // ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
+    // DEBUG_ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
 }

 template<HostLoc::Kind kind>
@@ -151,7 +151,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {

        return new_location_index;
    } else if constexpr (kind == HostLoc::Kind::Fpr) {
-        ASSERT(false && "Unimplemented instruction");
+        DEBUG_ASSERT(false && "Unimplemented instruction");
    } else {
        UNREACHABLE();
    }
@@ -165,15 +165,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
    }

    const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);

    if (current_location->kind == required_kind) {
        ValueInfo(*current_location).realized = true;
        return current_location->index;
    }

-    ASSERT(!ValueInfo(*current_location).realized);
-    ASSERT(!ValueInfo(*current_location).locked);
+    DEBUG_ASSERT(!ValueInfo(*current_location).realized);
+    DEBUG_ASSERT(!ValueInfo(*current_location).locked);

    if constexpr (required_kind == HostLoc::Kind::Gpr) {
        const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
@@ -236,7 +236,7 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kin
        }
    }

-    ASSERT(!ValueLocation(value));
+    DEBUG_ASSERT(!ValueLocation(value));

    const auto setup_location = [&](HostLocInfo& info) {
        info = {};
@@ -277,7 +277,7 @@ u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset
    std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) {
        return !hostloc_info[base_offset + i].locked;
    });
-    ASSERT(!candidates.empty());
+    DEBUG_ASSERT(!candidates.empty());

    u32 best = candidates[0];
    size_t min_lru = hostloc_info[base_offset + best].lru_counter;
@@ -294,7 +294,7 @@ u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset

 void RegAlloc::SpillGpr(u32 index) {
    auto& gpr_info = hostloc_info[GprOffset + index];
-    ASSERT(!gpr_info.locked && !gpr_info.realized);
+    DEBUG_ASSERT(!gpr_info.locked && !gpr_info.realized);
    if (gpr_info.values.empty()) {
        return;
    }
@@ -306,7 +306,7 @@ void RegAlloc::SpillGpr(u32 index) {

 void RegAlloc::SpillFpr(u32 index) {
    auto& fpr_info = hostloc_info[FprOffset + index];
-    ASSERT(!fpr_info.locked && !fpr_info.realized);
+    DEBUG_ASSERT(!fpr_info.locked && !fpr_info.realized);
    if (fpr_info.values.empty()) {
        return;
    }
@@ -94,7 +94,7 @@ void A32AddressSpace::EmitPrelude() {

 void A32AddressSpace::SetCursorPtr(CodePtr ptr) {
    ptrdiff_t offset = ptr - GetMemPtr<CodePtr>();
-    ASSERT(offset >= 0);
+    DEBUG_ASSERT(offset >= 0);
    as.RewindBuffer(offset);
 }

@@ -31,7 +31,7 @@ struct Jit::Impl final {
            , core(conf) {}

    HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        jit_interface->is_executing = true;
        HaltReason hr = core.Run(current_address_space, current_state, &halt_reason);
        RequestCacheInvalidation();
@@ -40,9 +40,9 @@ struct Jit::Impl final {
    }

    HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        jit_interface->is_executing = true;
-        ASSERT(false && "Unimplemented instruction");
+        DEBUG_ASSERT(false && "Unimplemented instruction");
        RequestCacheInvalidation();
        jit_interface->is_executing = false;
        return HaltReason{};
@@ -28,12 +28,12 @@ struct Jit::Impl final {
        , jit_interface(jit_interface) {}

    HaltReason Run() {
-        ASSERT(false);
+        DEBUG_ASSERT(false);
        return HaltReason{};
    }

    HaltReason Step() {
-        ASSERT(false);
+        DEBUG_ASSERT(false);
        return HaltReason{};
    }

@@ -51,7 +51,7 @@ struct Jit::Impl final {
    }

    void Reset() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        //jit_state = {};
    }

@@ -22,7 +22,7 @@ class CodeBlock {
 public:
    explicit CodeBlock(std::size_t size) noexcept : memsize(size) {
        mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
-        ASSERT(mem != nullptr);
+        DEBUG_ASSERT(mem != nullptr);
    }

    ~CodeBlock() noexcept {
@@ -35,39 +35,39 @@ void EmitIR<IR::Opcode::Identity>(biscuit::Assembler&, EmitContext& ctx, IR::Ins

 template<>
 void EmitIR<IR::Opcode::Breakpoint>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CallHostFunction>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PushRSB>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::GetCarryFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }

 template<>
 void EmitIR<IR::Opcode::GetOverflowFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::GetGEFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::GetNZCVFromOp>(biscuit::Assembler&, EmitContext& ctx, IR::Inst* inst) {
    [[maybe_unused]] auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(ctx.reg_alloc.IsValueLive(inst));
+    DEBUG_ASSERT(ctx.reg_alloc.IsValueLive(inst));
 }

 template<>
@@ -87,12 +87,12 @@ void EmitIR<IR::Opcode::GetNZFromOp>(biscuit::Assembler& as, EmitContext& ctx, I

 template<>
 void EmitIR<IR::Opcode::GetUpperFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::GetLowerFromOp>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -109,7 +109,7 @@ void EmitIR<IR::Opcode::GetCFlagFromNZCV>(biscuit::Assembler& as, EmitContext& c

 template<>
 void EmitIR<IR::Opcode::NZCVFromPackedFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitConfig& emit_conf) {
@@ -228,7 +228,7 @@ void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx) {

 template<>
 void EmitIR<IR::Opcode::A32SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -243,17 +243,17 @@ void EmitIR<IR::Opcode::A32GetRegister>(biscuit::Assembler& as, EmitContext& ctx

 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -272,27 +272,27 @@ void EmitIR<IR::Opcode::A32SetRegister>(biscuit::Assembler& as, EmitContext& ctx

 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetExtendedRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetVector>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetCpsr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -307,17 +307,17 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx

 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -325,7 +325,7 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

    // TODO: Add full implementation
-    ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
+    DEBUG_ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());

    auto Xnz = ctx.reg_alloc.ReadX(args[0]);
    auto Xc = ctx.reg_alloc.ReadX(args[1]);
@@ -341,82 +341,82 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,

 template<>
 void EmitIR<IR::Opcode::A32GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32OrQFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetGEFlags>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetGEFlagsCompressed>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32BXWritePC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32UpdateUpperLocationDescriptor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetFpscr>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32GetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32SetFpscrNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,37 +22,37 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::A32CoprocInternalOperation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocSendOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocSendTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocGetOneWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocGetTwoWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocLoadWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32CoprocStoreWords>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,87 +22,87 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::A32ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A32ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,182 +22,182 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::A64SetCheckBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetCFlag>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetNZCVRaw>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetW>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetX>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetS>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetD>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetSP>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetFPCR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetFPSR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetPC>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64CallSupervisor>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExceptionRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64DataCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64InstructionCacheOperationRaised>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64DataSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64DataMemoryBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64InstructionSynchronizationBarrier>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetCNTFRQ>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetCNTPCT>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetCTR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetDCZID>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64GetTPIDRRO>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64SetTPIDR>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,107 +22,107 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::A64ClearExclusive>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveReadMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64WriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64WriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64WriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64WriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64WriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::A64ExclusiveWriteMemory128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32Castagnoli64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32ISO8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32ISO16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32ISO32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CRC32ISO64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AESDecryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AESEncryptSingleRound>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AESInverseMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AESMixColumns>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SHA256Hash>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule0>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SHA256MessageSchedule1>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,67 +22,67 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::Pack2x32To1x64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Pack2x64To1x128>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LeastSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LeastSignificantHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LeastSignificantByte>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MostSignificantWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MostSignificantBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::IsZero32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::IsZero64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::TestBit>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ConditionalSelect32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ConditionalSelect64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ConditionalSelectNZCV>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -95,8 +95,8 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&
    auto& carry_arg = args[2];

    // TODO: Add full implementation
-    ASSERT(carry_inst != nullptr);
-    ASSERT(shift_arg.IsImmediate());
+    DEBUG_ASSERT(carry_inst != nullptr);
+    DEBUG_ASSERT(shift_arg.IsImmediate());

    auto Xresult = ctx.reg_alloc.WriteX(inst);
    auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);
@@ -124,7 +124,7 @@ void EmitIR<IR::Opcode::LogicalShiftLeft32>(biscuit::Assembler& as, EmitContext&

 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeft64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -136,8 +136,8 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext
    auto& shift_arg = args[1];

    // TODO: Add full implementation
-    ASSERT(carry_inst == nullptr);
-    ASSERT(shift_arg.IsImmediate());
+    DEBUG_ASSERT(carry_inst == nullptr);
+    DEBUG_ASSERT(shift_arg.IsImmediate());

    const u8 shift = shift_arg.GetImmediateU8();
    auto Xresult = ctx.reg_alloc.WriteX(inst);
@@ -153,72 +153,72 @@ void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext

 template<>
 void EmitIR<IR::Opcode::LogicalShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::BitRotateRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::BitRotateRight64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::RotateRightExtended>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LogicalShiftLeftMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::LogicalShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ArithmeticShiftRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::RotateRightMasked32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::RotateRightMasked64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<size_t bitsize>
@@ -264,7 +264,7 @@ static void AddImmWithFlags(biscuit::Assembler& as, biscuit::GPR rd, biscuit::GP
        as.SLLI(Xscratch1, Xscratch1, 28);
        as.OR(flags, flags, Xscratch1);
    } else {
-        ASSERT(false && "Unimplemented instruction");
+        DEBUG_ASSERT(false && "Unimplemented instruction");
    }
 }

@@ -279,7 +279,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
    auto Xa = ctx.reg_alloc.ReadX(args[0]);

    if (overflow_inst) {
-        ASSERT(false && "Unimplemented instruction");
+        DEBUG_ASSERT(false && "Unimplemented instruction");
    } else if (nzcv_inst) {
        if (args[1].IsImmediate()) {
            const u64 imm = args[1].GetImmediateU64();
@@ -294,17 +294,17 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                    AddImmWithFlags<bitsize>(as, *Xresult, *Xa, sub ? -imm : imm, *Xflags);
                }
            } else {
-                ASSERT(false && "Unimplemented instruction");
+                DEBUG_ASSERT(false && "Unimplemented instruction");
            }
        } else {
-            ASSERT(false && "Unimplemented instruction");
+            DEBUG_ASSERT(false && "Unimplemented instruction");
        }
    } else {
        if (args[1].IsImmediate()) {
            const u64 imm = args[1].GetImmediateU64();

            if (args[2].IsImmediate()) {
-                ASSERT(false && "Unimplemented instruction");
+                DEBUG_ASSERT(false && "Unimplemented instruction");
            } else {
                auto Xnzcv = ctx.reg_alloc.ReadX(args[2]);
                RegAlloc::Realize(Xresult, Xa, Xnzcv);
@@ -317,7 +317,7 @@ static void EmitAddSub(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst)
                as.ADDW(Xresult, Xa, Xscratch0);
            }
        } else {
-            ASSERT(false && "Unimplemented instruction");
+            DEBUG_ASSERT(false && "Unimplemented instruction");
        }
    }
 }
@@ -329,7 +329,7 @@ void EmitIR<IR::Opcode::Add32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins

 template<>
 void EmitIR<IR::Opcode::Add64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
@@ -339,237 +339,237 @@ void EmitIR<IR::Opcode::Sub32>(biscuit::Assembler& as, EmitContext& ctx, IR::Ins

 template<>
 void EmitIR<IR::Opcode::Sub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Mul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Mul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedMultiplyHigh64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::And32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::And64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AndNot32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::AndNot64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Eor32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Eor64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Or32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Or64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Not32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::Not64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendByteToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendHalfToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendWordToLong>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ZeroExtendLongToQuad>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ByteReverseWord>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ByteReverseHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ByteReverseDual>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::CountLeadingZeros64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ExtractRegister32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ExtractRegister64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ReplicateBit32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::ReplicateBit64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MaxSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MaxSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MaxUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MaxUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MinSigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MinSigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MinUnsigned32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::MinUnsigned64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,442 +22,442 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::FPAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPCompare32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPCompare64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipExponent16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipExponent32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipExponent64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToHalf>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPDoubleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPHalfToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedS64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPSingleToFixedU64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS16ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS32ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedU64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToDouble>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPFixedS64ToSingle>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,172 +22,172 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::PackedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingAddSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedHalvingSubAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedAddS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubU16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSaturatedSubS16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedAbsDiffSumU8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::PackedSelect>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,112 +22,112 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAddWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSubWithFlag32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturation>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::SignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,337 +22,337 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::FPVectorAbs16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorAbs32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorAbs64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorDiv32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorDiv64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorEqual16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorFromHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorFromSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorFromUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorGreater32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorGreater64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorGreaterEqual64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMax32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMax64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMaxNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMin32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMin64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMinNumeric64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMul32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMul64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMulAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMulX32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorMulX64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorNeg16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorNeg32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorNeg64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorPairedAddLower64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRecipStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRoundInt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtEstimate64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorRSqrtStepFused64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorSqrt64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToSignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::FPVectorToUnsignedFixed64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -22,82 +22,82 @@ namespace Dynarmic::Backend::RV64 {

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorSignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedAdd64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub8>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub16>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub32>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 template<>
 void EmitIR<IR::Opcode::VectorUnsignedSaturatedSub64>(biscuit::Assembler&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "Unimplemented instruction");
+    DEBUG_ASSERT(false && "Unimplemented instruction");
 }

 }  // namespace Dynarmic::Backend::RV64
@@ -44,19 +44,19 @@ bool Argument::GetImmediateU1() const {

 u8 Argument::GetImmediateU8() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100);
+    DEBUG_ASSERT(imm < 0x100);
    return u8(imm);
 }

 u16 Argument::GetImmediateU16() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x10000);
+    DEBUG_ASSERT(imm < 0x10000);
    return u16(imm);
 }

 u32 Argument::GetImmediateU32() const {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm < 0x100000000);
+    DEBUG_ASSERT(imm < 0x100000000);
    return u32(imm);
 }

@@ -65,12 +65,12 @@ u64 Argument::GetImmediateU64() const {
 }

 IR::Cond Argument::GetImmediateCond() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
    return value.GetCond();
 }

 IR::AccType Argument::GetImmediateAccType() const {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
    return value.GetAccType();
 }

@@ -79,7 +79,7 @@ bool HostLocInfo::Contains(const IR::Inst* value) const {
 }

 void HostLocInfo::SetupScratchLocation() {
-    ASSERT(IsCompletelyEmpty());
+    DEBUG_ASSERT(IsCompletelyEmpty());
    realized = true;
 }

@@ -104,7 +104,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
        const IR::Value arg = inst->GetArg(i);
        ret[i].value = arg;
        if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
+            DEBUG_ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
            ValueInfo(arg.GetInst()).uses_this_inst++;
        }
    }
@@ -128,7 +128,7 @@ void RegAlloc::UpdateAllUses() {
 }

 void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
-    ASSERT(!ValueLocation(inst));
+    DEBUG_ASSERT(!ValueLocation(inst));

    if (arg.value.IsImmediate()) {
        inst->ReplaceUsesWith(arg.value);
@@ -142,15 +142,15 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {

 void RegAlloc::AssertNoMoreUses() const {
    const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
-    ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
-    ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
-    ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
+    DEBUG_ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
+    DEBUG_ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
+    DEBUG_ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
 }

 template<HostLoc::Kind kind>
 u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
    // TODO
-    // ASSERT(value.GetType() != IR::Type::U1);
+    // DEBUG_ASSERT(value.GetType() != IR::Type::U1);

    if constexpr (kind == HostLoc::Kind::Gpr) {
        const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -161,7 +161,7 @@ u32 RegAlloc::GenerateImmediate(const IR::Value& value) {

        return new_location_index;
    } else if constexpr (kind == HostLoc::Kind::Fpr) {
-        ASSERT(false && "Unimplemented instruction");
+        DEBUG_ASSERT(false && "Unimplemented instruction");
    } else {
        UNREACHABLE();
    }
@@ -175,15 +175,15 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
    }

    const auto current_location = ValueLocation(value.GetInst());
-    ASSERT(current_location);
+    DEBUG_ASSERT(current_location);

    if (current_location->kind == required_kind) {
        ValueInfo(*current_location).realized = true;
        return current_location->index;
    }

-    ASSERT(!ValueInfo(*current_location).realized);
-    ASSERT(!ValueInfo(*current_location).locked);
+    DEBUG_ASSERT(!ValueInfo(*current_location).realized);
+    DEBUG_ASSERT(!ValueInfo(*current_location).locked);

    if constexpr (required_kind == HostLoc::Kind::Gpr) {
        const u32 new_location_index = AllocateRegister(gprs, gpr_order);
@@ -194,7 +194,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
            UNREACHABLE(); //logic error
        case HostLoc::Kind::Fpr:
            as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
-            // ASSERT size fits
+            // DEBUG_ASSERT size fits
            break;
        case HostLoc::Kind::Spill:
            as.LD(biscuit::GPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
@@ -229,7 +229,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {

 template<HostLoc::Kind required_kind>
 u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
-    ASSERT(!ValueLocation(value));
+    DEBUG_ASSERT(!ValueLocation(value));

    const auto setup_location = [&](HostLocInfo& info) {
        info = {};
@@ -274,7 +274,7 @@ u32 RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
 }

 void RegAlloc::SpillGpr(u32 index) {
-    ASSERT(!gprs[index].locked && !gprs[index].realized);
+    DEBUG_ASSERT(!gprs[index].locked && !gprs[index].realized);
    if (gprs[index].values.empty()) {
        return;
    }
@@ -284,7 +284,7 @@ void RegAlloc::SpillGpr(u32 index) {
 }

 void RegAlloc::SpillFpr(u32 index) {
-    ASSERT(!fprs[index].locked && !fprs[index].realized);
+    DEBUG_ASSERT(!fprs[index].locked && !fprs[index].realized);
    if (fprs[index].values.empty()) {
        return;
    }
@@ -295,7 +295,7 @@ void RegAlloc::SpillFpr(u32 index) {

 u32 RegAlloc::FindFreeSpill() const {
    const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT(iter != spills.end() && "All spill locations are full");
+    DEBUG_ASSERT(iter != spills.end() && "All spill locations are full");
    return static_cast<u32>(iter - spills.begin());
 }

@@ -209,11 +209,11 @@ void A32EmitX64::InvalidateCacheRanges(const boost::icl::interval_set<u32>& rang

 void A32EmitX64::EmitCondPrelude(const A32EmitContext& ctx) {
    if (ctx.block.GetCondition() == IR::Cond::AL) {
-        ASSERT(!ctx.block.HasConditionFailedLocation());
+        DEBUG_ASSERT(!ctx.block.HasConditionFailedLocation());
        return;
    }

-    ASSERT(ctx.block.HasConditionFailedLocation());
+    DEBUG_ASSERT(ctx.block.HasConditionFailedLocation());

    Xbyak::Label pass = EmitCond(ctx.block.GetCondition());
    if (conf.enable_cycle_counting) {
@@ -311,7 +311,7 @@ void A32EmitX64::EmitA32GetRegister(A32EmitContext& ctx, IR::Inst* inst) {

 void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    DEBUG_ASSERT(A32::IsSingleExtReg(reg));

    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    code.movss(result, MJitStateExtReg(reg));
@@ -320,7 +320,7 @@ void A32EmitX64::EmitA32GetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins

 void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));

    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    code.movsd(result, MJitStateExtReg(reg));
@@ -329,7 +329,7 @@ void A32EmitX64::EmitA32GetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins

 void A32EmitX64::EmitA32GetVector(A32EmitContext& ctx, IR::Inst* inst) {
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));

    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    if (A32::IsDoubleExtReg(reg)) {
@@ -358,7 +358,7 @@ void A32EmitX64::EmitA32SetRegister(A32EmitContext& ctx, IR::Inst* inst) {
 void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsSingleExtReg(reg));
+    DEBUG_ASSERT(A32::IsSingleExtReg(reg));

    if (args[1].IsInXmm(ctx.reg_alloc)) {
        Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -372,7 +372,7 @@ void A32EmitX64::EmitA32SetExtendedRegister32(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg));

    if (args[1].IsInXmm(ctx.reg_alloc)) {
        const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -386,7 +386,7 @@ void A32EmitX64::EmitA32SetExtendedRegister64(A32EmitContext& ctx, IR::Inst* ins
 void A32EmitX64::EmitA32SetVector(A32EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));

    const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[1]);
    if (A32::IsDoubleExtReg(reg)) {
@@ -647,7 +647,7 @@ void A32EmitX64::EmitA32GetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {

 void A32EmitX64::EmitA32SetGEFlags(A32EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(!args[0].IsImmediate());
+    DEBUG_ASSERT(!args[0].IsImmediate());

    if (args[0].IsInXmm(ctx.reg_alloc)) {
        const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(code, args[0]);
@@ -788,7 +788,7 @@ void A32EmitX64::EmitA32ExceptionRaised(A32EmitContext& ctx, IR::Inst* inst) {
    ctx.reg_alloc.EndOfAllocScope();

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    DEBUG_ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
    const u32 pc = args[0].GetImmediateU32();
    const u64 exception = args[1].GetImmediateU64();
    Devirtualize<&A32::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {
@@ -74,7 +74,7 @@ struct Jit::Impl {
    ~Impl() = default;

    HaltReason Run() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
        jit_interface->is_executing = true;
        const CodePtr current_codeptr = [this] {
@@ -94,7 +94,7 @@ struct Jit::Impl {
    }

    HaltReason Step() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
        jit_interface->is_executing = true;
        const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ struct Jit::Impl {
    }

    void Reset() {
-        ASSERT(!jit_interface->is_executing);
+        DEBUG_ASSERT(!jit_interface->is_executing);
        jit_state = {};
    }

@@ -501,7 +501,7 @@ void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
    ctx.reg_alloc.HostCall(code, nullptr);
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    DEBUG_ASSERT(args[0].IsImmediate());
    const u32 imm = args[0].GetImmediateU32();
    Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, [&](RegList param) {
        code.mov(param[0], imm);
@@ -513,7 +513,7 @@ void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
 void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
    ctx.reg_alloc.HostCall(code, nullptr);
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
+    DEBUG_ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
    const u64 pc = args[0].GetImmediateU64();
    const u64 exception = args[1].GetImmediateU64();
    Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) {
@@ -66,13 +66,13 @@ public:
        , emitter(block_of_code, conf, jit)
        , polyfill_options(GenPolyfillOptions(block_of_code))
    {
-        ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
+        DEBUG_ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64);
    }

    ~Impl() = default;

    HaltReason Run() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
        is_executing = true;
        // TODO: Check code alignment
@@ -92,7 +92,7 @@ public:
    }

    HaltReason Step() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        PerformRequestedCacheInvalidation(static_cast<HaltReason>(Atomic::Load(&jit_state.halt_reason)));
        is_executing = true;
        const HaltReason hr = block_of_code.StepCode(&jit_state, GetCurrentSingleStep());
@@ -116,7 +116,7 @@ public:
    }

    void Reset() {
-        ASSERT(!is_executing);
+        DEBUG_ASSERT(!is_executing);
        jit_state = {};
    }

@@ -191,12 +191,12 @@ void BlockOfCode::DisableWriting() {
 }

 void BlockOfCode::ClearCache() {
-    ASSERT(prelude_complete);
+    DEBUG_ASSERT(prelude_complete);
    SetCodePtr(code_begin);
 }

 size_t BlockOfCode::SpaceRemaining() const {
-    ASSERT(prelude_complete);
+    DEBUG_ASSERT(prelude_complete);
    const u8* current_ptr = getCurr<const u8*>();
    if (current_ptr >= &top_[maxSize_])
        return 0;
@@ -466,7 +466,7 @@ void BlockOfCode::SetCodePtr(CodePtr code_ptr) {

 void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) {
    size_t current_size = getCurr<const u8*>() - reinterpret_cast<const u8*>(begin);
-    ASSERT(current_size <= size);
+    DEBUG_ASSERT(current_size <= size);
    nop(size - current_size);
 }

@@ -28,7 +28,7 @@ Xbyak::Address ConstantPool::GetConstant(BlockOfCode& code, const Xbyak::Address
    const auto constant = ConstantT(lower, upper);
    auto it = constant_info.find(constant);
    if (it == constant_info.end()) {
-        ASSERT(insertion_point < pool.size());
+        DEBUG_ASSERT(insertion_point < pool.size());
        ConstantT& target_constant = pool[insertion_point];
        target_constant = constant;
        it = constant_info.insert({constant, &target_constant}).first;
@@ -148,7 +148,7 @@ void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc) {

 void EmitX64::EmitPushRSB(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[0].IsImmediate());
+    DEBUG_ASSERT(args[0].IsImmediate());
    const u64 unique_hash_of_target = args[0].GetImmediateU64();

    ctx.reg_alloc.ScratchGpr(code, HostLoc::RCX);
@@ -288,7 +288,7 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) {
 }

 void EmitX64::EmitAddCycles(size_t cycles) {
-    ASSERT(cycles < (std::numeric_limits<s32>::max)());
+    DEBUG_ASSERT(cycles < (std::numeric_limits<s32>::max)());
    code.sub(qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, cycles_remaining)], static_cast<u32>(cycles));
 }

@@ -129,7 +129,7 @@ void EmitX64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitTestBit(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    // TODO: Flag optimization
    code.bt(result, args[1].GetImmediateU8());
    code.setc(result.cvt8());
@@ -1842,7 +1842,7 @@ void EmitX64::EmitFPFixedS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
    if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
        code.cvtsi2ss(result, from);
    } else {
-        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
        code.EnterStandardASIMD();
        code.cvtsi2ss(result, from);
        code.LeaveStandardASIMD();
@@ -1878,7 +1878,7 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
    if (rounding_mode == ctx.FPCR().RMode() || ctx.HasOptimization(OptimizationFlag::Unsafe_IgnoreStandardFPCRValue)) {
        op();
    } else {
-        ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+        DEBUG_ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
        code.EnterStandardASIMD();
        op();
        code.LeaveStandardASIMD();
@@ -1984,7 +1984,7 @@ void EmitX64::EmitFPFixedS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    const size_t fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());

    code.cvtsi2sd(result, from);

@@ -2003,7 +2003,7 @@ void EmitX64::EmitFPFixedS64ToSingle(EmitContext& ctx, IR::Inst* inst) {
    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    const size_t fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());

    code.cvtsi2ss(result, from);

@@ -2022,7 +2022,7 @@ void EmitX64::EmitFPFixedU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    const size_t fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());

    if (code.HasHostFeature(HostFeature::AVX512F)) {
        code.vcvtusi2sd(result, result, from);
@@ -2053,7 +2053,7 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) {
    const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(code);
    const size_t fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
-    ASSERT(rounding_mode == ctx.FPCR().RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR().RMode());

    if (code.HasHostFeature(HostFeature::AVX512F)) {
        const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(code, args[0]);
@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 /* This file is part of the dynarmic project.
 * Copyright (c) 2022 MerryMage
 * SPDX-License-Identifier: 0BSD
@@ -113,7 +116,7 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) {
        });
    } else {
        // Use page table
-        ASSERT(conf.page_table);
+        DEBUG_ASSERT(conf.page_table);
        const auto src_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
        EmitReadMemoryMov<bitsize>(code, value_idx, src_ptr, ordered);

@@ -200,7 +203,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {
        });
    } else {
        // Use page table
-        ASSERT(conf.page_table);
+        DEBUG_ASSERT(conf.page_table);
        const auto dest_ptr = EmitVAddrLookup(code, ctx, bitsize, *abort, vaddr);
        EmitWriteMemoryMov<bitsize>(code, dest_ptr, value_idx, ordered);

@@ -216,7 +219,7 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) {

 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor != nullptr);
+    DEBUG_ASSERT(conf.global_monitor != nullptr);
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const bool ordered = IsOrdered(args[2].GetImmediateAccType());

@@ -267,7 +270,7 @@ void AxxEmitX64::EmitExclusiveReadMemory(AxxEmitContext& ctx, IR::Inst* inst) {

 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor != nullptr);
+    DEBUG_ASSERT(conf.global_monitor != nullptr);
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const bool ordered = IsOrdered(args[3].GetImmediateAccType());

@@ -320,7 +323,7 @@ void AxxEmitX64::EmitExclusiveWriteMemory(AxxEmitContext& ctx, IR::Inst* inst) {

 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    DEBUG_ASSERT(conf.global_monitor && conf.fastmem_pointer);
    if (!exception_handler.SupportsFastmem()) {
        EmitExclusiveReadMemory<bitsize, callback>(ctx, inst);
        return;
@@ -397,7 +400,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in

 template<std::size_t bitsize, auto callback>
 void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* inst) {
-    ASSERT(conf.global_monitor && conf.fastmem_pointer);
+    DEBUG_ASSERT(conf.global_monitor && conf.fastmem_pointer);
    if (!exception_handler.SupportsFastmem()) {
        EmitExclusiveWriteMemory<bitsize, callback>(ctx, inst);
        return;
@@ -148,7 +148,7 @@ template<>
            code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
        }
    } else {
-        ASSERT(valid_page_index_bits < 32);
+        DEBUG_ASSERT(valid_page_index_bits < 32);
        code.mov(tmp, vaddr);
        code.shr(tmp, int(page_table_const_bits));
        code.test(tmp, u32(-(1 << valid_page_index_bits)));
@@ -118,7 +118,7 @@ void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const size_t N = args[1].GetImmediateU8();
-    ASSERT(N >= 1 && N <= 32);
+    DEBUG_ASSERT(N >= 1 && N <= 32);

    if (N == 32) {
        if (overflow_inst) {
@@ -167,7 +167,7 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) {

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    const size_t N = args[1].GetImmediateU8();
-    ASSERT(N <= 31);
+    DEBUG_ASSERT(N <= 31);

    const u32 saturated_value = (1u << N) - 1;

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@@ -18,7 +18,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {

    const bool part1 = args[3].GetImmediateU1();

-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));

    //      3   2   1   0
    // x =  d   c   b   a
@@ -54,7 +54,7 @@ void EmitX64::EmitSHA256Hash(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));

    const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
    const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -67,7 +67,7 @@ void EmitX64::EmitSHA256MessageSchedule0(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitSHA256MessageSchedule1(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

-    ASSERT(code.HasHostFeature(HostFeature::SHA));
+    DEBUG_ASSERT(code.HasHostFeature(HostFeature::SHA));

    const Xbyak::Xmm x = ctx.reg_alloc.UseScratchXmm(code, args[0]);
    const Xbyak::Xmm y = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -177,7 +177,7 @@ static void EmitTwoArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Ins

 void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    // TODO: DefineValue directly on Argument for index == 0
@@ -201,7 +201,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    // TODO: DefineValue directly on Argument for index == 0
@@ -214,7 +214,7 @@ void EmitX64::EmitVectorGetElement16(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    // TODO: DefineValue directly on Argument for index == 0
@@ -235,7 +235,7 @@ void EmitX64::EmitVectorGetElement32(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    if (index == 0) {
@@ -263,7 +263,7 @@ void EmitX64::EmitVectorGetElement64(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
    auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);

@@ -295,7 +295,7 @@ void EmitX64::EmitVectorSetElement8(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();

    auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);
@@ -308,7 +308,7 @@ void EmitX64::EmitVectorSetElement16(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
    auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);

@@ -331,7 +331,7 @@ void EmitX64::EmitVectorSetElement32(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorSetElement64(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
    auto const source_vector = ctx.reg_alloc.UseScratchXmm(code, args[0]);

@@ -717,9 +717,9 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 16);
+    DEBUG_ASSERT(index < 16);
    if (index > 0) {
        code.psrldq(a, index);
    }
@@ -741,9 +741,9 @@ void EmitX64::EmitVectorBroadcastElementLower8(EmitContext& ctx, IR::Inst* inst)
 void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 8);
+    DEBUG_ASSERT(index < 8);
    if (index > 0) {
        code.psrldq(a, u8(index * 2));
    }
@@ -754,9 +754,9 @@ void EmitX64::EmitVectorBroadcastElementLower16(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 4);
+    DEBUG_ASSERT(index < 4);

    if (index > 0) {
        code.psrldq(a, u8(index * 4));
@@ -770,9 +770,9 @@ void EmitX64::EmitVectorBroadcastElementLower32(EmitContext& ctx, IR::Inst* inst
 void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 16);
+    DEBUG_ASSERT(index < 16);
    if (index > 0) {
        code.psrldq(a, index);
    }
@@ -794,9 +794,9 @@ void EmitX64::EmitVectorBroadcastElement8(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 8);
+    DEBUG_ASSERT(index < 8);
    if (index == 0 && code.HasHostFeature(HostFeature::AVX2)) {
        code.vpbroadcastw(a, a);
    } else {
@@ -814,9 +814,9 @@ void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 4);
+    DEBUG_ASSERT(index < 4);

    code.pshufd(a, a, mcl::bit::replicate_element<2, u8>(index));

@@ -826,9 +826,9 @@ void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) {
 void EmitX64::EmitVectorBroadcastElement64(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto const a = ctx.reg_alloc.UseScratchXmm(code, args[0]);
-    ASSERT(args[1].IsImmediate());
+    DEBUG_ASSERT(args[1].IsImmediate());
    const u8 index = args[1].GetImmediateU8();
-    ASSERT(index < 2);
+    DEBUG_ASSERT(index < 2);

    if (code.HasHostFeature(HostFeature::AVX)) {
        code.vpermilpd(a, a, mcl::bit::replicate_element<1, u8>(index));
@@ -1314,7 +1314,7 @@ void EmitX64::EmitVectorExtract(EmitContext& ctx, IR::Inst* inst) {
    auto args = ctx.reg_alloc.GetArgumentInfo(inst);

    const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    DEBUG_ASSERT(position % 8 == 0);

    if (position == 0) {
        ctx.reg_alloc.DefineValue(code, inst, args[0]);
@@ -1346,7 +1346,7 @@ void EmitX64::EmitVectorExtractLower(EmitContext& ctx, IR::Inst* inst) {
    auto const xmm_a = ctx.reg_alloc.UseScratchXmm(code, args[0]);

    const u8 position = args[2].GetImmediateU8();
-    ASSERT(position % 8 == 0);
+    DEBUG_ASSERT(position % 8 == 0);

    if (position != 0) {
        auto const xmm_b = ctx.reg_alloc.UseXmm(code, args[1]);
@@ -3821,7 +3821,7 @@ void EmitX64::EmitVectorRotateWholeVectorRight(EmitContext& ctx, IR::Inst* inst)
    auto const operand = ctx.reg_alloc.UseXmm(code, args[0]);
    auto const result = ctx.reg_alloc.ScratchXmm(code);
    const u8 shift_amount = args[1].GetImmediateU8();
-    ASSERT(shift_amount % 32 == 0);
+    DEBUG_ASSERT(shift_amount % 32 == 0);
    const u8 shuffle_imm = std::rotr<u8>(0b11100100, shift_amount / 32 * 2);

    code.pshufd(result, operand, shuffle_imm);
@@ -4914,7 +4914,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
        code.punpcklbw(reconstructed, xmm0);
        break;
    case 32:
-        ASSERT(code.HasHostFeature(HostFeature::SSE41));
+        DEBUG_ASSERT(code.HasHostFeature(HostFeature::SSE41));
        code.packusdw(dest, xmm0);  // SSE4.1
        code.movdqa(reconstructed, dest);
        code.punpcklwd(reconstructed, xmm0);
@@ -5276,11 +5276,11 @@ void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) {

 void EmitX64::EmitVectorTable(EmitContext&, IR::Inst* inst) {
    // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
+    DEBUG_ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }

 void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -5438,7 +5438,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
            code.pxor(xmm0, xmm0);
            code.punpcklqdq(xmm_table1, xmm0);
        } else {
-            ASSERT(table_size == 4);
+            DEBUG_ASSERT(table_size == 4);
            auto const xmm_table1_upper = ctx.reg_alloc.UseXmm(code, table[3]);
            code.punpcklqdq(xmm_table1, xmm_table1_upper);
            ctx.reg_alloc.Release(xmm_table1_upper);
@@ -5529,7 +5529,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {
 }

 void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);
+    DEBUG_ASSERT(inst->GetArg(1).GetInst()->GetOpcode() == IR::Opcode::VectorTable);

    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
    auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst());
@@ -676,7 +676,7 @@ void EmitX64::EmitFPVectorFromSignedFixed32(EmitContext& ctx, IR::Inst* inst) {
    const int fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
    const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        code.cvtdq2ps(xmm, xmm);
@@ -694,7 +694,7 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) {
    const int fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
    const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {
@@ -745,7 +745,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst)
    const int fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
    const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        if (code.HasHostFeature(HostFeature::AVX512_Ortho)) {
@@ -795,7 +795,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst)
    const int fbits = args[1].GetImmediateU8();
    const FP::RoundingMode rounding_mode = static_cast<FP::RoundingMode>(args[2].GetImmediateU8());
    const bool fpcr_controlled = args[3].GetImmediateU1();
-    ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());
+    DEBUG_ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode());

    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
        if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) {
@@ -104,7 +104,7 @@ static PrologueInformation GetPrologueInformation() {
        entry.code.OpInfo = reg;
    };
    const auto alloc_large = [&](u8 offset, size_t size) {
-        ASSERT(size % 8 == 0);
+        DEBUG_ASSERT(size % 8 == 0);
        size /= 8;

        auto& entry = next_entry();
@@ -123,7 +123,7 @@ static PrologueInformation GetPrologueInformation() {
        }
    };
    const auto save_xmm128 = [&](u8 offset, u8 reg, size_t frame_offset) {
-        ASSERT(frame_offset % 16 == 0);
+        DEBUG_ASSERT(frame_offset % 16 == 0);

        auto& entry = next_entry();
        entry.code.CodeOffset = offset;
@@ -165,7 +165,7 @@ static PrologueInformation GetPrologueInformation() {
        auto& last_entry = next_entry();
        last_entry.FrameOffset = 0;
    }
-    ASSERT(ret.unwind_code.size() % 2 == 0);
+    DEBUG_ASSERT(ret.unwind_code.size() % 2 == 0);

    return ret;
 }
@@ -78,12 +78,12 @@ constexpr bool HostLocIsFlag(HostLoc reg) {
 }

 constexpr HostLoc HostLocRegIdx(int idx) {
-    ASSERT(idx >= 0 && idx <= 15);
+    DEBUG_ASSERT(idx >= 0 && idx <= 15);
    return HostLoc(idx);
 }

 constexpr HostLoc HostLocXmmIdx(int idx) {
-    ASSERT(idx >= 0 && idx <= 15);
+    DEBUG_ASSERT(idx >= 0 && idx <= 15);
    return HostLoc(size_t(HostLoc::XMM0) + idx);
 }

@@ -159,12 +159,12 @@ const std::bitset<32> any_xmm = BuildRegSet({
 });

 inline Xbyak::Reg64 HostLocToReg64(HostLoc loc) noexcept {
-    ASSERT(HostLocIsGPR(loc));
+    DEBUG_ASSERT(HostLocIsGPR(loc));
    return Xbyak::Reg64(int(loc));
 }

 inline Xbyak::Xmm HostLocToXmm(HostLoc loc) noexcept {
-    ASSERT(HostLocIsXMM(loc));
+    DEBUG_ASSERT(HostLocIsXMM(loc));
    return Xbyak::Xmm(int(loc) - int(HostLoc::XMM0));
 }

@@ -56,11 +56,11 @@ static inline bool IsValuelessType(const IR::Type type) noexcept {
 }

 void HostLocInfo::ReleaseOne() noexcept {
-    ASSERT(is_being_used_count > 0);
+    DEBUG_ASSERT(is_being_used_count > 0);
    --is_being_used_count;
    is_scratch = false;
    if (current_references > 0) {
-        ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+        DEBUG_ASSERT(size_t(accumulated_uses) + 1 < (std::numeric_limits<decltype(accumulated_uses)>::max)());
        ++accumulated_uses;
        --current_references;
        if (current_references == 0)
@@ -69,7 +69,7 @@ void HostLocInfo::ReleaseOne() noexcept {
 }

 void HostLocInfo::ReleaseAll() noexcept {
-    ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
+    DEBUG_ASSERT(size_t(accumulated_uses) + current_references < (std::numeric_limits<decltype(accumulated_uses)>::max)());
    accumulated_uses += current_references;
    current_references = 0;
    is_set_last_use = false;
@@ -91,7 +91,7 @@ void HostLocInfo::AddValue(HostLoc loc, IR::Inst* inst) noexcept {
    }
    values.push_back(inst);

-    ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
+    DEBUG_ASSERT(size_t(total_uses) + inst->UseCount() < (std::numeric_limits<decltype(total_uses)>::max)());
    total_uses += inst->UseCount();
    max_bit_width = std::max<uint8_t>(max_bit_width, std::countr_zero(GetBitWidth(inst->GetType())));
 }
@@ -129,24 +129,24 @@ bool Argument::GetImmediateU1() const noexcept {

 u8 Argument::GetImmediateU8() const noexcept {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
+    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u8>::max()));
    return u8(imm);
 }

 u16 Argument::GetImmediateU16() const noexcept {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
+    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u16>::max()));
    return u16(imm);
 }

 u32 Argument::GetImmediateU32() const noexcept {
    const u64 imm = value.GetImmediateAsU64();
-    ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
+    DEBUG_ASSERT(imm <= u64(std::numeric_limits<u32>::max()));
    return u32(imm);
 }

 u64 Argument::GetImmediateS32() const noexcept {
-    ASSERT(FitsInImmediateS32());
+    DEBUG_ASSERT(FitsInImmediateS32());
    return value.GetImmediateAsU64();
 }

@@ -155,12 +155,12 @@ u64 Argument::GetImmediateU64() const noexcept {
 }

 IR::Cond Argument::GetImmediateCond() const noexcept {
-    ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
    return value.GetCond();
 }

 IR::AccType Argument::GetImmediateAccType() const noexcept {
-    ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
+    DEBUG_ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
    return value.GetAccType();
 }

@@ -201,7 +201,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
        ret[i].value = arg;
        if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
            auto const loc = ValueLocation(arg.GetInst());
-            ASSERT(loc && "argument must already been defined");
+            DEBUG_ASSERT(loc && "argument must already been defined");
            LocInfo(*loc).AddArgReference();
        }
    }
@@ -209,7 +209,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
 }

 void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
-    ASSERT(IsValueLive(inst) || !inst->HasUses());
+    DEBUG_ASSERT(IsValueLive(inst) || !inst->HasUses());
    for (size_t i = 0; i < inst->NumArgs(); i++) {
        auto const arg = inst->GetArg(i);
        if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
@@ -222,37 +222,37 @@ void RegAlloc::RegisterPseudoOperation(const IR::Inst* inst) noexcept {
 }

 Xbyak::Reg64 RegAlloc::UseScratchGpr(BlockOfCode& code, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    DEBUG_ASSERT(!arg.allocated);
    arg.allocated = true;
    return HostLocToReg64(UseScratchImpl(code, arg.value, gpr_order));
 }

 Xbyak::Xmm RegAlloc::UseScratchXmm(BlockOfCode& code, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    DEBUG_ASSERT(!arg.allocated);
    arg.allocated = true;
    return HostLocToXmm(UseScratchImpl(code, arg.value, xmm_order));
 }

 void RegAlloc::UseScratch(BlockOfCode& code, Argument& arg, HostLoc host_loc) noexcept {
-    ASSERT(!arg.allocated);
+    DEBUG_ASSERT(!arg.allocated);
    arg.allocated = true;
    UseScratchImpl(code, arg.value, BuildRegSet({host_loc}));
 }

 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, const Xbyak::Reg& reg) noexcept {
-    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    DEBUG_ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
    const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
    DefineValueImpl(code, inst, hostloc);
 }

 void RegAlloc::DefineValue(BlockOfCode& code, IR::Inst* inst, Argument& arg) noexcept {
-    ASSERT(!arg.allocated);
+    DEBUG_ASSERT(!arg.allocated);
    arg.allocated = true;
    DefineValueImpl(code, inst, arg.value);
 }

 void RegAlloc::Release(const Xbyak::Reg& reg) noexcept {
-    ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
+    DEBUG_ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
    const auto hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
    LocInfo(hostloc).ReleaseOne();
 }
@@ -382,15 +382,15 @@ void RegAlloc::HostCall(
 }

 void RegAlloc::AllocStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    ASSERT(reserved_stack_space == 0);
+    DEBUG_ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    DEBUG_ASSERT(reserved_stack_space == 0);
    reserved_stack_space = stack_space;
    code.sub(code.rsp, u32(stack_space));
 }

 void RegAlloc::ReleaseStackSpace(BlockOfCode& code, const size_t stack_space) noexcept {
-    ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
-    ASSERT(reserved_stack_space == stack_space);
+    DEBUG_ASSERT(stack_space < size_t((std::numeric_limits<s32>::max)()));
+    DEBUG_ASSERT(reserved_stack_space == stack_space);
    reserved_stack_space = 0;
    code.add(code.rsp, u32(stack_space));
 }
@@ -449,7 +449,7 @@ HostLoc RegAlloc::SelectARegister(std::bitset<32> desired_locations) const noexc
    auto const it_final = it_empty_candidate != HostLoc::FirstSpill
        ? it_empty_candidate : it_candidate != HostLoc::FirstSpill
        ? it_candidate : it_rex_candidate;
-    ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
+    DEBUG_ASSERT(it_final != HostLoc::FirstSpill && "All candidate registers have already been allocated");
    // Evil magic - increment LRU counter (will wrap at 256)
    const_cast<RegAlloc*>(this)->LocInfo(HostLoc(it_final)).lru_counter++;
    return HostLoc(it_final);
@@ -459,26 +459,26 @@ std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const noex
    for (size_t i = 0; i < hostloc_info.size(); i++)
        if (hostloc_info[i].ContainsValue(value)) {
            //for (size_t j = 0; j < hostloc_info.size(); ++j)
-            //    ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
+            //    DEBUG_ASSERT((i == j || !hostloc_info[j].ContainsValue(value)) && "duplicate defs");
            return HostLoc(i);
        }
    return std::nullopt;
 }

 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, HostLoc host_loc) noexcept {
-    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    DEBUG_ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
    LocInfo(host_loc).AddValue(host_loc, def_inst);
-    ASSERT(*ValueLocation(def_inst) == host_loc);
+    DEBUG_ASSERT(*ValueLocation(def_inst) == host_loc);
 }

 void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::Value& use_inst) noexcept {
-    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
+    DEBUG_ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
    if (use_inst.IsImmediate()) {
        const HostLoc location = ScratchImpl(code, gpr_order);
        DefineValueImpl(code, def_inst, location);
        LoadImmediate(code, use_inst, location);
    } else {
-        ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
+        DEBUG_ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
        const HostLoc location = *ValueLocation(use_inst.GetInst());
        DefineValueImpl(code, def_inst, location);
    }
@@ -486,22 +486,22 @@ void RegAlloc::DefineValueImpl(BlockOfCode& code, IR::Inst* def_inst, const IR::

 void RegAlloc::Move(BlockOfCode& code, HostLoc to, HostLoc from) noexcept {
    const size_t bit_width = LocInfo(from).GetMaxBitWidth();
-    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
-    ASSERT(bit_width <= HostLocBitWidth(to));
-    ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
+    DEBUG_ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
+    DEBUG_ASSERT(bit_width <= HostLocBitWidth(to));
+    DEBUG_ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
    EmitMove(code, bit_width, to, from);
    LocInfo(to) = std::exchange(LocInfo(from), {});
 }

 void RegAlloc::CopyToScratch(BlockOfCode& code, size_t bit_width, HostLoc to, HostLoc from) noexcept {
-    ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
+    DEBUG_ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
    EmitMove(code, bit_width, to, from);
 }

 void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
-    ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
-    ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
-    ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
+    DEBUG_ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
+    DEBUG_ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
+    DEBUG_ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));

    if (LocInfo(a).IsEmpty()) {
        Move(code, a, b);
@@ -514,16 +514,16 @@ void RegAlloc::Exchange(BlockOfCode& code, HostLoc a, HostLoc b) noexcept {
 }

 void RegAlloc::MoveOutOfTheWay(BlockOfCode& code, HostLoc reg) noexcept {
-    ASSERT(!LocInfo(reg).IsLocked());
+    DEBUG_ASSERT(!LocInfo(reg).IsLocked());
    if (!LocInfo(reg).IsEmpty()) {
        SpillRegister(code, reg);
    }
 }

 void RegAlloc::SpillRegister(BlockOfCode& code, HostLoc loc) noexcept {
-    ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
-    ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
-    ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
+    DEBUG_ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
+    DEBUG_ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
+    DEBUG_ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
    auto const new_loc = FindFreeSpill(HostLocIsXMM(loc));
    Move(code, new_loc, loc);
 }
@@ -559,7 +559,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
    }()

 HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_loc) noexcept {
-    ASSERT(imm.IsImmediate() && "imm is not an immediate");
+    DEBUG_ASSERT(imm.IsImmediate() && "imm is not an immediate");
    if (HostLocIsGPR(host_loc)) {
        const Xbyak::Reg64 reg = HostLocToReg64(host_loc);
        const u64 imm_value = imm.GetImmediateAsU64();
@@ -584,9 +584,9 @@ HostLoc RegAlloc::LoadImmediate(BlockOfCode& code, IR::Value imm, HostLoc host_l

 void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc to, const HostLoc from) noexcept {
    auto const spill_to_op_arg_helper = [&](HostLoc loc, size_t reserved_stack_space) {
-        ASSERT(HostLocIsSpill(loc));
+        DEBUG_ASSERT(HostLocIsSpill(loc));
        size_t i = size_t(loc) - size_t(HostLoc::FirstSpill);
-        ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
+        DEBUG_ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
        return Xbyak::util::rsp + reserved_stack_space + ABI_SHADOW_SPACE + offsetof(StackLayout, spill) + i * sizeof(StackLayout::spill[0]);
    };
    auto const spill_xmm_to_op = [&](const HostLoc loc) {
@@ -595,21 +595,21 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
    if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
        MAYBE_AVX(movaps, HostLocToXmm(to), HostLocToXmm(from));
    } else if (HostLocIsGPR(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        DEBUG_ASSERT(bit_width != 128);
        if (bit_width == 64) {
            code.mov(HostLocToReg64(to), HostLocToReg64(from));
        } else {
            code.mov(HostLocToReg64(to).cvt32(), HostLocToReg64(from).cvt32());
        }
    } else if (HostLocIsXMM(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        DEBUG_ASSERT(bit_width != 128);
        if (bit_width == 64) {
            MAYBE_AVX(movq, HostLocToXmm(to), HostLocToReg64(from));
        } else {
            MAYBE_AVX(movd, HostLocToXmm(to), HostLocToReg64(from).cvt32());
        }
    } else if (HostLocIsGPR(to) && HostLocIsXMM(from)) {
-        ASSERT(bit_width != 128);
+        DEBUG_ASSERT(bit_width != 128);
        if (bit_width == 64) {
            MAYBE_AVX(movq, HostLocToReg64(to), HostLocToXmm(from));
        } else {
@@ -617,7 +617,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
        }
    } else if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
        const Xbyak::Address spill_addr = spill_xmm_to_op(from);
-        ASSERT(spill_addr.getBit() >= bit_width);
+        DEBUG_ASSERT(spill_addr.getBit() >= bit_width);
        switch (bit_width) {
        case 128:
            MAYBE_AVX(movaps, HostLocToXmm(to), spill_addr);
@@ -635,7 +635,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
        }
    } else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
        const Xbyak::Address spill_addr = spill_xmm_to_op(to);
-        ASSERT(spill_addr.getBit() >= bit_width);
+        DEBUG_ASSERT(spill_addr.getBit() >= bit_width);
        switch (bit_width) {
        case 128:
            MAYBE_AVX(movaps, spill_addr, HostLocToXmm(from));
@@ -652,14 +652,14 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
            UNREACHABLE();
        }
    } else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
-        ASSERT(bit_width != 128);
+        DEBUG_ASSERT(bit_width != 128);
        if (bit_width == 64) {
            code.mov(HostLocToReg64(to), Xbyak::util::qword[spill_to_op_arg_helper(from, reserved_stack_space)]);
        } else {
            code.mov(HostLocToReg64(to).cvt32(), Xbyak::util::dword[spill_to_op_arg_helper(from, reserved_stack_space)]);
        }
    } else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
-        ASSERT(bit_width != 128);
+        DEBUG_ASSERT(bit_width != 128);
        if (bit_width == 64) {
            code.mov(Xbyak::util::qword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from));
        } else {
@@ -672,7 +672,7 @@ void RegAlloc::EmitMove(BlockOfCode& code, const size_t bit_width, const HostLoc
 #undef MAYBE_AVX

 void RegAlloc::EmitExchange(BlockOfCode& code, const HostLoc a, const HostLoc b) noexcept {
-    ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
+    DEBUG_ASSERT(HostLocIsGPR(a) && HostLocIsGPR(b) && "Exchanging XMM registers is uneeded OR invalid emit");
    code.xchg(HostLocToReg64(a), HostLocToReg64(b));
 }

@@ -49,19 +49,19 @@ public:
        return is_being_used_count == 0 && current_references == 1 && size_t(accumulated_uses) + 1 == size_t(total_uses);
    }
    inline void ReadLock() noexcept {
-        ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
-        ASSERT(!bool(is_scratch));
+        DEBUG_ASSERT(size_t(is_being_used_count) + 1 < (std::numeric_limits<decltype(is_being_used_count)>::max)());
+        DEBUG_ASSERT(!bool(is_scratch));
        is_being_used_count++;
    }
    inline void WriteLock() noexcept {
-        ASSERT(is_being_used_count == 0);
+        DEBUG_ASSERT(is_being_used_count == 0);
        is_being_used_count++;
        is_scratch = true;
    }
    inline void AddArgReference() noexcept {
-        ASSERT(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
+        DEBUG_ASSERT(size_t(current_references) + 1 < (std::numeric_limits<decltype(current_references)>::max)());
        ++current_references;
-        ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses));
+        DEBUG_ASSERT(size_t(accumulated_uses) + current_references <= size_t(total_uses));
    }
    void ReleaseOne() noexcept;
    void ReleaseAll() noexcept;
@@ -147,12 +147,12 @@ public:
        return !!ValueLocation(inst);
    }
    inline Xbyak::Reg64 UseGpr(BlockOfCode& code, Argument& arg) noexcept {
-        ASSERT(!arg.allocated);
+        DEBUG_ASSERT(!arg.allocated);
        arg.allocated = true;
        return HostLocToReg64(UseImpl(code, arg.value, gpr_order));
    }
    inline Xbyak::Xmm UseXmm(BlockOfCode& code, Argument& arg) noexcept {
-        ASSERT(!arg.allocated);
+        DEBUG_ASSERT(!arg.allocated);
        arg.allocated = true;
        return HostLocToXmm(UseImpl(code, arg.value, xmm_order));
    }
@@ -160,7 +160,7 @@ public:
        return UseGpr(code, arg);
    }
    inline void Use(BlockOfCode& code, Argument& arg, const HostLoc host_loc) noexcept {
-        ASSERT(!arg.allocated);
+        DEBUG_ASSERT(!arg.allocated);
        arg.allocated = true;
        UseImpl(code, arg.value, BuildRegSet({host_loc}));
    }
@@ -205,7 +205,7 @@ public:
            iter.ReleaseAll();
    }
    inline void AssertNoMoreUses() noexcept {
-        ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
+        DEBUG_ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) noexcept { return i.IsEmpty(); }));
    }
 #ifndef NDEBUG
    inline void EmitVerboseDebuggingOutput(BlockOfCode& code) noexcept {
@@ -73,7 +73,7 @@ public:

    /// Set rounding mode control field.
    void RMode(FP::RoundingMode rounding_mode) {
-        ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
+        DEBUG_ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
        value = mcl::bit::set_bits<22, 23>(value, static_cast<u32>(rounding_mode));
    }

@@ -93,7 +93,7 @@ public:
    /// Set the stride of a vector when executing AArch32 VFP instructions.
    /// This field has no function in AArch64 state.
    void Stride(size_t stride) {
-        ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
+        DEBUG_ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
        value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u);
    }

@@ -116,7 +116,7 @@ public:
    /// Sets the length of a vector when executing AArch32 VFP instructions.
    /// This field has no function in AArch64 state.
    void Len(size_t len) {
-        ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
+        DEBUG_ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
        value = mcl::bit::set_bits<16, 18>(value, static_cast<u32>(len - 1));
    }

@@ -26,7 +26,7 @@ namespace Dynarmic::FP {

 template<typename FPT>
 u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) {
-    ASSERT(rounding != RoundingMode::ToOdd);
+    DEBUG_ASSERT(rounding != RoundingMode::ToOdd);

    auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);

@@ -25,9 +25,9 @@ namespace Dynarmic::FP {

 template<typename FPT>
 u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    ASSERT(rounding != RoundingMode::ToOdd);
-    ASSERT(ibits <= 64);
-    ASSERT(fbits <= ibits);
+    DEBUG_ASSERT(rounding != RoundingMode::ToOdd);
+    DEBUG_ASSERT(ibits <= 64);
+    DEBUG_ASSERT(fbits <= ibits);

    auto [type, sign, value] = FPUnpack<FPT>(op, fpcr, fpsr);

@@ -18,27 +18,27 @@ namespace Dynarmic::FP {
 void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
    switch (exception) {
    case FPExc::InvalidOp:
-        ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.IOE() && "Raising floating point exceptions unimplemented");
        fpsr.IOC(true);
        break;
    case FPExc::DivideByZero:
-        ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.DZE() && "Raising floating point exceptions unimplemented");
        fpsr.DZC(true);
        break;
    case FPExc::Overflow:
-        ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.OFE() && "Raising floating point exceptions unimplemented");
        fpsr.OFC(true);
        break;
    case FPExc::Underflow:
-        ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.UFE() && "Raising floating point exceptions unimplemented");
        fpsr.UFC(true);
        break;
    case FPExc::Inexact:
-        ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.IXE() && "Raising floating point exceptions unimplemented");
        fpsr.IXC(true);
        break;
    case FPExc::InputDenorm:
-        ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
+        DEBUG_ASSERT(!fpcr.IDE() && "Raising floating point exceptions unimplemented");
        fpsr.IDC(true);
        break;
    default:
@@ -23,7 +23,7 @@ namespace Dynarmic::FP {

 template<typename FPT>
 FPT FPProcessNaN(FPType type, FPT op, FPCR fpcr, FPSR& fpsr) {
-    ASSERT(type == FPType::QNaN || type == FPType::SNaN);
+    DEBUG_ASSERT(type == FPType::QNaN || type == FPType::SNaN);

    constexpr size_t topfrac = FPInfo<FPT>::explicit_mantissa_width - 1;

@@ -85,8 +85,8 @@ std::tuple<bool, int, u64, ResidualError> Normalize(FPUnpacked op, int extra_rig

 template<typename FPT>
 FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) {
-    ASSERT(op.mantissa != 0);
-    ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero);
+    DEBUG_ASSERT(op.mantissa != 0);
+    DEBUG_ASSERT(rounding != RoundingMode::ToNearest_TieAwayFromZero);

    constexpr int minimum_exp = FPInfo<FPT>::exponent_min;
    constexpr size_t E = FPInfo<FPT>::exponent_width;
@@ -35,7 +35,7 @@ std::string DisassembleX64(const void* begin, const void* end) {
    while (pos < end) {
        char buffer[80];
        size_t inst_size = LLVMDisasmInstruction(llvm_ctx, const_cast<u8*>(pos), remaining, reinterpret_cast<u64>(pos), buffer, sizeof(buffer));
-        ASSERT(inst_size);
+        DEBUG_ASSERT(inst_size);
        for (const u8* i = pos; i < pos + inst_size; i++)
            result += fmt::format("{:02x} ", *i);
        for (size_t i = inst_size; i < 10; i++)
@@ -64,12 +64,12 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
 }

 IR::U128 IREmitter::GetVector(ExtReg reg) {
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
    return Inst<IR::U128>(Opcode::A32GetVector, IR::Value(reg));
 }

 void IREmitter::SetRegister(const Reg reg, const IR::U32& value) {
-    ASSERT(reg != A32::Reg::PC);
+    DEBUG_ASSERT(reg != A32::Reg::PC);
    Inst(Opcode::A32SetRegister, IR::Value(reg), value);
 }

@@ -84,7 +84,7 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
 }

 void IREmitter::SetVector(ExtReg reg, const IR::U128& value) {
-    ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
+    DEBUG_ASSERT(A32::IsDoubleExtReg(reg) || A32::IsQuadExtReg(reg));
    Inst(Opcode::A32SetVector, IR::Value(reg), value);
 }

@@ -361,7 +361,7 @@ IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& v
 }

 void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(opc1),
@@ -373,7 +373,7 @@ void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1,
 }

 void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(opc1),
@@ -384,7 +384,7 @@ void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, Copro
 }

 void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(opc),
@@ -393,7 +393,7 @@ void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, Copro
 }

 IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(opc1),
@@ -404,7 +404,7 @@ IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, Cop
 }

 IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(opc),
@@ -413,7 +413,7 @@ IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, Cop
 }

 void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(long_transfer ? 1 : 0),
@@ -424,7 +424,7 @@ void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer,
 }

 void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
-    ASSERT(coproc_no <= 15);
+    DEBUG_ASSERT(coproc_no <= 15);
    const IR::Value::CoprocessorInfo coproc_info{static_cast<u8>(coproc_no),
                                                 static_cast<u8>(two ? 1 : 0),
                                                 static_cast<u8>(long_transfer ? 1 : 0),
@@ -85,7 +85,7 @@ constexpr bool IsQuadExtReg(ExtReg reg) {
 }

 inline size_t RegNumber(Reg reg) {
-    ASSERT(reg != Reg::INVALID_REG);
+    DEBUG_ASSERT(reg != Reg::INVALID_REG);
    return size_t(reg);
 }

@@ -95,13 +95,13 @@ inline size_t RegNumber(ExtReg reg) {
    } else if (IsDoubleExtReg(reg)) {
        return size_t(reg) - size_t(ExtReg::D0);
    }
-    ASSERT(IsQuadExtReg(reg));
+    DEBUG_ASSERT(IsQuadExtReg(reg));
    return size_t(reg) - size_t(ExtReg::Q0);
 }

 inline Reg operator+(Reg reg, size_t number) {
    const size_t new_reg = RegNumber(reg) + number;
-    ASSERT(new_reg <= 15);
+    DEBUG_ASSERT(new_reg <= 15);

    return static_cast<Reg>(new_reg);
 }
@@ -109,7 +109,7 @@ inline Reg operator+(Reg reg, size_t number) {
 inline ExtReg operator+(ExtReg reg, size_t number) {
    const auto new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);

-    ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg))
+    DEBUG_ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg))
           || (IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg))
           || (IsQuadExtReg(reg) && IsQuadExtReg(new_reg)));

@@ -21,7 +21,7 @@
 namespace Dynarmic::A32 {

 bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir) {
-    ASSERT(cond_state != ConditionalState::Break && "Should never happen.");
+    DEBUG_ASSERT(cond_state != ConditionalState::Break && "Should never happen.");
    if (cond_state == ConditionalState::None)
        return true;

@@ -32,7 +32,7 @@ bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir
 }

 bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) {
-    ASSERT(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored.");
+    DEBUG_ASSERT(v.cond_state != ConditionalState::Break && "This should never happen. We requested a break but that wasn't honored.");

    if (cond == IR::Cond::NV) {
        // NV conditional is obsolete
@@ -29,7 +29,7 @@ bool TranslatorVisitor::ThumbConditionPassed() {

 bool TranslatorVisitor::VFPConditionPassed(Cond cond) {
    if (ir.current_location.TFlag()) {
-        ASSERT(cond == Cond::AL);
+        DEBUG_ASSERT(cond == Cond::AL);
        return true;
    }
    return ArmConditionPassed(cond);
@@ -130,7 +130,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b
            }
            return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
        case Narrowing::SaturateToSigned:
-            ASSERT(signedness == Signedness::Signed);
+            DEBUG_ASSERT(signedness == Signedness::Signed);
            return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
        }
        UNREACHABLE();
@@ -95,7 +95,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
        return UnpredictableInstruction();
    }

-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if ((!P || W) && n == t) {
        return UnpredictableInstruction();
    }
@@ -126,7 +126,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
 // LDR <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDR <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (m == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -184,7 +184,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
        return UnpredictableInstruction();
    }

-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if ((!P || W) && n == t) {
        return UnpredictableInstruction();
    }
@@ -209,7 +209,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (t == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -352,7 +352,7 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R

 // LDRH <Rt>, [PC, #-/+<imm>]
 bool TranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (P == W) {
        return UnpredictableInstruction();
    }
@@ -382,7 +382,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
        return UnpredictableInstruction();
    }

-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if ((!P || W) && n == t) {
        return UnpredictableInstruction();
    }
@@ -407,7 +407,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (t == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -456,7 +456,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
        return UnpredictableInstruction();
    }

-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if ((!P || W) && n == t) {
        return UnpredictableInstruction();
    }
@@ -481,7 +481,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (t == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -529,7 +529,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
        return UnpredictableInstruction();
    }

-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if ((!P || W) && n == t) {
        return UnpredictableInstruction();
    }
@@ -554,7 +554,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT(!(!P && W) && "T form of instruction unimplemented");
+    DEBUG_ASSERT(!(!P && W) && "T form of instruction unimplemented");
    if (t == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -34,7 +34,7 @@ bool TranslatorVisitor::arm_MRS(Cond cond, Reg d) {

 // MSR<c> <spec_reg>, #<const>
 bool TranslatorVisitor::arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) {
-    ASSERT(mask != 0 && "Decode error");
+    DEBUG_ASSERT(mask != 0 && "Decode error");

    if (!ArmConditionPassed(cond)) {
        return true;
@@ -687,7 +687,7 @@ bool TranslatorVisitor::thumb16_NOP() {

 // IT{<x>{<y>{<z>}}} <cond>
 bool TranslatorVisitor::thumb16_IT(Imm<8> imm8) {
-    ASSERT((imm8.Bits<0, 3>() != 0b0000) && "Decode Error");
+    DEBUG_ASSERT((imm8.Bits<0, 3>() != 0b0000) && "Decode Error");
    if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && std::popcount(imm8.Bits<0, 3>()) != 1)) {
        return UnpredictableInstruction();
    }
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }

 bool TranslatorVisitor::thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");
    if ((d == Reg::PC && !S) || n == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -69,7 +69,7 @@ bool TranslatorVisitor::thumb32_MOV_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }

 bool TranslatorVisitor::thumb32_ORR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(n != Reg::PC && "Decode error");
+    DEBUG_ASSERT(n != Reg::PC && "Decode error");
    if (d == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -100,7 +100,7 @@ bool TranslatorVisitor::thumb32_MVN_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }

 bool TranslatorVisitor::thumb32_ORN_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(n != Reg::PC && "Decode error");
+    DEBUG_ASSERT(n != Reg::PC && "Decode error");
    if (d == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -128,7 +128,7 @@ bool TranslatorVisitor::thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }

 bool TranslatorVisitor::thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");
    if ((d == Reg::PC && !S) || n == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -156,7 +156,7 @@ bool TranslatorVisitor::thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }

 bool TranslatorVisitor::thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");
    if ((d == Reg::PC && !S) || n == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -214,7 +214,7 @@ bool TranslatorVisitor::thumb32_CMP_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }

 bool TranslatorVisitor::thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");
    if ((d == Reg::PC && !S) || n == Reg::PC) {
        return UnpredictableInstruction();
    }
@@ -17,7 +17,7 @@ namespace Dynarmic::A32 {
 using SaturationFunction = IR::ResultAndOverflow<IR::U32> (IREmitter::*)(const IR::U32&, size_t);

 static bool Saturation(TranslatorVisitor& v, bool sh, Reg n, Reg d, Imm<5> shift_amount, size_t saturate_to, SaturationFunction sat_fn) {
-    ASSERT(!(sh && shift_amount == 0) && "Invalid decode");
+    DEBUG_ASSERT(!(sh && shift_amount == 0) && "Invalid decode");

    if (d == Reg::PC || n == Reg::PC) {
        return v.UnpredictableInstruction();
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@@ -23,7 +23,7 @@ bool TranslatorVisitor::thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }

 bool TranslatorVisitor::thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");

    if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -67,7 +67,7 @@ bool TranslatorVisitor::thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }

 bool TranslatorVisitor::thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(n != Reg::PC && "Decode error");
+    DEBUG_ASSERT(n != Reg::PC && "Decode error");

    if (d == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -97,7 +97,7 @@ bool TranslatorVisitor::thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }

 bool TranslatorVisitor::thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(n != Reg::PC && "Decode error");
+    DEBUG_ASSERT(n != Reg::PC && "Decode error");

    if (d == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -125,7 +125,7 @@ bool TranslatorVisitor::thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }

 bool TranslatorVisitor::thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");

    if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -168,7 +168,7 @@ bool TranslatorVisitor::thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }

 bool TranslatorVisitor::thumb32_ADD_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");

    if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -224,7 +224,7 @@ bool TranslatorVisitor::thumb32_CMP_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }

 bool TranslatorVisitor::thumb32_SUB_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT(!(d == Reg::PC && S) && "Decode error");
+    DEBUG_ASSERT(!(d == Reg::PC && S) && "Decode error");

    if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
        return UnpredictableInstruction();
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later

 /* This file is part of the dynarmic project.
@@ -1304,11 +1304,11 @@ bool TranslatorVisitor::vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bo
 // VSTM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
    if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p == u && w) {
@@ -1356,11 +1356,11 @@ bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VSTM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
    if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p == u && w) {
@@ -1399,11 +1399,11 @@ bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
    if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p == u && w) {
@@ -1449,11 +1449,11 @@ bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
    if (!p && !u && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p && !w) {
-        ASSERT(false && "Decode error");
+        DEBUG_ASSERT(false && "Decode error");
    }

    if (p == u && w) {
@@ -73,7 +73,7 @@ void TranslateArm(IR::Block& block, LocationDescriptor descriptor, TranslateCall
            }
        }
    }
-    ASSERT(block.HasTerminal() && "Terminal has not been set");
+    DEBUG_ASSERT(block.HasTerminal() && "Terminal has not been set");
    block.SetEndLocation(visitor.ir.current_location);
 }

@@ -172,7 +172,7 @@ void TranslateThumb(IR::Block& block, LocationDescriptor descriptor, TranslateCa
            }
        }
    }
-    ASSERT(block.HasTerminal() && "Terminal has not been set");
+    DEBUG_ASSERT(block.HasTerminal() && "Terminal has not been set");
    block.SetEndLocation(visitor.ir.current_location);
 }

@@ -114,14 +114,14 @@ constexpr size_t VecNumber(Vec vec) {

 inline Reg operator+(Reg reg, size_t number) {
    const size_t new_reg = RegNumber(reg) + number;
-    ASSERT(new_reg <= 31);
+    DEBUG_ASSERT(new_reg <= 31);

    return static_cast<Reg>(new_reg);
 }

 inline Vec operator+(Vec vec, size_t number) {
    const size_t new_vec = VecNumber(vec) + number;
-    ASSERT(new_vec <= 31);
+    DEBUG_ASSERT(new_vec <= 31);

    return static_cast<Vec>(new_vec);
 }
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
lizzie	5679d20e2a	2026-09-11 20:03:41 Signed-off-by: lizzie <lizzie@eden-emu.dev>	2026-09-11 20:03:41 +00:00
lizzie	64cec648f5	2026-09-11 19:36:26 Signed-off-by: lizzie <lizzie@eden-emu.dev>	2026-09-11 19:36:26 +00:00
lizzie	ea11b44946	2026-09-11 19:25:01 Signed-off-by: lizzie <lizzie@eden-emu.dev>	2026-09-11 19:25:01 +00:00