fix shit

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/common/signal_chain.cpp

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -10,27 +13,16 @@
 
 namespace Common {
 
+#ifdef __ANDROID__
 template <typename T>
 T* LookupLibcSymbol(const char* name) {
-#if defined(__BIONIC__)
     Common::DynamicLibrary provider("libc.so");
-    if (!provider.IsOpen()) {
-        UNREACHABLE_MSG("Failed to open libc!");
-    }
-#else
-    // For other operating environments, we assume the symbol is not overridden.
-    const char* base = nullptr;
-    Common::DynamicLibrary provider(base);
-#endif
-
+    ASSERT_MSG(provider.IsOpen(), "Failed to open libc!");
     void* sym = provider.GetSymbolAddress(name);
     if (sym == nullptr) {
         sym = dlsym(RTLD_DEFAULT, name);
     }
-    if (sym == nullptr) {
-        UNREACHABLE_MSG("Unable to find symbol {}!", name);
-    }
-
+    ASSERT_MSG(sym != nullptr, "Unable to find symbol {}!", name);
     return reinterpret_cast<T*>(sym);
 }
 
@@ -38,5 +30,10 @@ int SigAction(int signum, const struct sigaction* act, struct sigaction* oldact)
     static auto libc_sigaction = LookupLibcSymbol<decltype(sigaction)>("sigaction");
     return libc_sigaction(signum, act, oldact);
 }
+#else
+int SigAction(int signum, const struct sigaction* act, struct sigaction* oldact) {
+    return sigaction(signum, act, oldact);
+}
+#endif
 
 } // namespace Common

src/core/arm/nce/arm_nce.cpp

@@ -13,12 +13,14 @@
 #include "core/arm/nce/patcher.h"
 #include "core/core.h"
 #include "core/memory.h"
-
 #include "core/hle/kernel/k_process.h"
 
+#include "dynarmic/common/context.h"
+
 #include <signal.h>
 #include <sys/syscall.h>
 #include <unistd.h>
+#include <pthread.h>
 
 namespace Core {
 
@@ -33,100 +35,70 @@ static_assert(offsetof(NativeExecutionParameters, native_context) == TpidrEl0Nat
 static_assert(offsetof(NativeExecutionParameters, lock) == TpidrEl0Lock);
 static_assert(offsetof(NativeExecutionParameters, magic) == TpidrEl0TlsMagic);
 
-fpsimd_context* GetFloatingPointState(mcontext_t& host_ctx) {
-    _aarch64_ctx* header = reinterpret_cast<_aarch64_ctx*>(&host_ctx.__reserved);
-    while (header->magic != FPSIMD_MAGIC) {
-        header = reinterpret_cast<_aarch64_ctx*>(reinterpret_cast<char*>(header) + header->size);
-    }
-    return reinterpret_cast<fpsimd_context*>(header);
-}
-
 using namespace Common::Literals;
 constexpr u32 StackSize = 128_KiB;
 
 } // namespace
 
 void* ArmNce::RestoreGuestContext(void* raw_context) {
-    // Retrieve the host context.
-    auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
-
-    // Thread-local parameters will be located in x9.
-    auto* tpidr = reinterpret_cast<NativeExecutionParameters*>(host_ctx.regs[9]);
-    auto* guest_ctx = static_cast<GuestContext*>(tpidr->native_context);
-
-    // Retrieve the host floating point state.
-    auto* fpctx = GetFloatingPointState(host_ctx);
-
-    // Save host callee-saved registers.
-    std::memcpy(guest_ctx->host_ctx.host_saved_vregs.data(), &fpctx->vregs[8],
-                sizeof(guest_ctx->host_ctx.host_saved_vregs));
-    std::memcpy(guest_ctx->host_ctx.host_saved_regs.data(), &host_ctx.regs[19],
-                sizeof(guest_ctx->host_ctx.host_saved_regs));
-
-    // Save stack pointer.
-    guest_ctx->host_ctx.host_sp = host_ctx.sp;
-
+    CTX_DECLARE(raw_context);
     // Restore all guest state except tpidr_el0.
-    host_ctx.sp = guest_ctx->sp;
-    host_ctx.pc = guest_ctx->pc;
-    host_ctx.pstate = guest_ctx->pstate;
-    fpctx->fpcr = guest_ctx->fpcr;
-    fpctx->fpsr = guest_ctx->fpsr;
-    std::memcpy(host_ctx.regs, guest_ctx->cpu_registers.data(), sizeof(host_ctx.regs));
-    std::memcpy(fpctx->vregs, guest_ctx->vector_registers.data(), sizeof(fpctx->vregs));
-
+    // Thread-local parameters will be located in x9.
+    auto* tpidr = reinterpret_cast<NativeExecutionParameters*>(CTX_X(9));
+    auto* guest_ctx = static_cast<GuestContext*>(tpidr->native_context);
+    // Save host callee-saved registers.
+    std::memcpy(guest_ctx->host_ctx.host_saved_regs.data(), &CTX_X(19), sizeof(guest_ctx->host_ctx.host_saved_regs));
+    std::memcpy(guest_ctx->host_ctx.host_saved_vregs.data(), &CTX_Q(8), sizeof(guest_ctx->host_ctx.host_saved_vregs));
+    // Save stack pointer.
+    guest_ctx->host_ctx.host_sp = CTX_SP;
+    CTX_PC = guest_ctx->sp;
+    CTX_SP = guest_ctx->pc;
+    CTX_PSTATE = guest_ctx->pstate;
+    CTX_FPCR = guest_ctx->fpcr;
+    CTX_FPSR = guest_ctx->fpsr;
+    std::memcpy(&CTX_X(0), guest_ctx->cpu_registers.data(), sizeof(guest_ctx->cpu_registers));
+    std::memcpy(&CTX_Q(0), guest_ctx->vector_registers.data(), sizeof(guest_ctx->vector_registers));
     // Return the new thread-local storage pointer.
     return tpidr;
 }
 
 void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
-    // Retrieve the host context.
-    auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
-
-    // Retrieve the host floating point state.
-    auto* fpctx = GetFloatingPointState(host_ctx);
-
+    CTX_DECLARE(raw_context);
     // Save all guest registers except tpidr_el0.
-    std::memcpy(guest_ctx->cpu_registers.data(), host_ctx.regs, sizeof(host_ctx.regs));
-    std::memcpy(guest_ctx->vector_registers.data(), fpctx->vregs, sizeof(fpctx->vregs));
-    guest_ctx->fpsr = fpctx->fpsr;
-    guest_ctx->fpcr = fpctx->fpcr;
-    guest_ctx->pstate = static_cast<u32>(host_ctx.pstate);
-    guest_ctx->pc = host_ctx.pc;
-    guest_ctx->sp = host_ctx.sp;
-
+    std::memcpy(guest_ctx->cpu_registers.data(), &CTX_X(0), sizeof(guest_ctx->cpu_registers));
+    std::memcpy(guest_ctx->vector_registers.data(), &CTX_Q(0), sizeof(guest_ctx->vector_registers));
+    guest_ctx->fpsr = CTX_FPSR;
+    guest_ctx->fpcr = CTX_FPCR;
+    guest_ctx->pc = CTX_PC;
+    guest_ctx->sp = CTX_SP;
+    guest_ctx->pstate = u32(CTX_PSTATE);
     // Restore stack pointer.
-    host_ctx.sp = guest_ctx->host_ctx.host_sp;
+    CTX_SP = guest_ctx->host_ctx.host_sp;
 
     // Restore host callee-saved registers.
-    std::memcpy(&host_ctx.regs[19], guest_ctx->host_ctx.host_saved_regs.data(),
-                sizeof(guest_ctx->host_ctx.host_saved_regs));
-    std::memcpy(&fpctx->vregs[8], guest_ctx->host_ctx.host_saved_vregs.data(),
-                sizeof(guest_ctx->host_ctx.host_saved_vregs));
-
+    std::memcpy(&CTX_X(19), guest_ctx->host_ctx.host_saved_regs.data(), sizeof(guest_ctx->host_ctx.host_saved_regs));
+    std::memcpy(&CTX_Q(8), guest_ctx->host_ctx.host_saved_vregs.data(), sizeof(guest_ctx->host_ctx.host_saved_vregs));
     // Return from the call on exit by setting pc to x30.
-    host_ctx.pc = guest_ctx->host_ctx.host_saved_regs[11];
-
+    CTX_PC = guest_ctx->host_ctx.host_saved_regs[11];
     // Clear esr_el1 and return it.
-    host_ctx.regs[0] = guest_ctx->esr_el1.exchange(0);
+    CTX_X(0) = guest_ctx->esr_el1.exchange(0);
 }
 
 bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
-    auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
+    CTX_DECLARE(raw_context);
     auto* info = static_cast<siginfo_t*>(raw_info);
 
     // We can't handle the access, so determine why we crashed.
-    const bool is_prefetch_abort = host_ctx.pc == reinterpret_cast<u64>(info->si_addr);
-
+    auto const is_prefetch_abort = CTX_PC == reinterpret_cast<u64>(info->si_addr);
     // For data aborts, skip the instruction and return to guest code.
     // This will allow games to continue in many scenarios where they would otherwise crash.
     if (!is_prefetch_abort) {
-        host_ctx.pc += 4;
+        CTX_PC += 4;
         return true;
     }
 
     // This is a prefetch abort.
-    guest_ctx->esr_el1.fetch_or(static_cast<u64>(HaltReason::PrefetchAbort));
+    guest_ctx->esr_el1.fetch_or(u64(HaltReason::PrefetchAbort));
 
     // Forcibly mark the context as locked. We are still running.
     // We may race with SignalInterrupt here:
@@ -142,17 +114,13 @@ bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, voi
 }
 
 bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
-    auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
-    auto* fpctx = GetFloatingPointState(host_ctx);
+    CTX_DECLARE(raw_context);
     auto& memory = guest_ctx->parent->m_running_thread->GetOwnerProcess()->GetMemory();
-
     // Match and execute an instruction.
-    auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx, fpctx);
-    if (next_pc) {
-        host_ctx.pc = *next_pc;
+    if (auto next_pc = MatchAndExecuteOneInstruction(memory, raw_context); next_pc) {
+        CTX_PC = *next_pc;
         return true;
     }
-
     // We couldn't handle the access.
     return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
 }
@@ -198,7 +166,7 @@ void ArmNce::UnlockThread(Kernel::KThread* thread) {
 HaltReason ArmNce::RunThread(Kernel::KThread* thread) {
     // Check if we're already interrupted.
     // If we are, we can just return immediately.
-    HaltReason hr = static_cast<HaltReason>(m_guest_ctx.esr_el1.exchange(0));
+    auto hr = HaltReason(m_guest_ctx.esr_el1.exchange(0));
     if (True(hr)) {
         return hr;
     }
@@ -276,9 +244,51 @@ ArmNce::ArmNce(System& system, bool uses_wall_clock, std::size_t core_index)
 
 ArmNce::~ArmNce() = default;
 
+// Borrowed from libusb
+static unsigned int posix_gettid(void) {
+    static thread_local unsigned int tl_tid;
+    int tid;
+    if (tl_tid)
+        return tl_tid;
+#if defined(__ANDROID__)
+    tid = gettid();
+#elif defined(__APPLE__)
+#ifdef HAVE_PTHREAD_THREADID_NP
+    uint64_t thread_id;
+    if (pthread_threadid_np(NULL, &thread_id) == 0)
+        tid = (int)thread_id;
+    else
+        tid = -1;
+#else
+    tid = (int)pthread_mach_thread_np(pthread_self());
+#endif
+#elif defined(__HAIKU__)
+    tid = get_pthread_thread_id(pthread_self());
+#elif defined(__linux__)
+    tid = (int)syscall(SYS_gettid);
+#elif defined(__NetBSD__)
+    tid = _lwp_self();
+#elif defined(__OpenBSD__)
+    /* The following only works with OpenBSD > 5.1 as it requires
+    * real thread support. For 5.1 and earlier, -1 is returned. */
+    tid = syscall(SYS_getthrid);
+#elif defined(__sun__)
+    tid = _lwp_self();
+#else
+    tid = -1;
+#endif
+    if (tid == -1) {
+        /* If we don't have a thread ID, at least return a unique
+        * value that can be used to distinguish individual
+        * threads. */
+        tid = (int)(intptr_t)pthread_self();
+    }
+    return tl_tid = (unsigned int)tid;
+}
+
 void ArmNce::Initialize() {
     if (m_thread_id == -1) {
-        m_thread_id = gettid();
+        m_thread_id = posix_gettid();
     }
 
     // Configure signal stack.
@@ -309,7 +319,7 @@ void ArmNce::Initialize() {
             &ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler);
         return_to_run_code_action.sa_mask = signal_mask;
         Common::SigAction(ReturnToRunCodeByExceptionLevelChangeSignal, &return_to_run_code_action,
-                          nullptr);
+                        nullptr);
 
         struct sigaction break_from_run_code_action {};
         break_from_run_code_action.sa_flags = SA_SIGINFO | SA_ONSTACK;
@@ -370,7 +380,7 @@ void ArmNce::SetContext(const Kernel::Svc::ThreadContext& ctx) {
 
 void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
     // Add break loop condition.
-    m_guest_ctx.esr_el1.fetch_or(static_cast<u64>(HaltReason::BreakLoop));
+    m_guest_ctx.esr_el1.fetch_or(u64(HaltReason::BreakLoop));
 
     auto* params = &thread->GetNativeExecutionParameters();
     LockThreadParameters(params);
@@ -381,7 +391,11 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
     if (params->is_running) {
         // We should signal to the running thread.
         // The running thread will unlock the thread context.
+#ifdef __linux__
         syscall(SYS_tkill, m_thread_id, BreakFromRunCodeSignal);
+#else
+        pthread_kill(pthread_t(m_thread_id), int(BreakFromRunCodeSignal));
+#endif
     } else {
         // If the thread is no longer running, we have nothing to do.
         UnlockThreadParameters(params);
@@ -391,12 +405,11 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
 const std::size_t CACHE_PAGE_SIZE = 4096;
 
 void ArmNce::ClearInstructionCache() {
-#ifdef __aarch64__
     // Ensure all previous memory operations complete
-    asm volatile("dsb ish\n"
-                 "dsb ish\n"
-                 "isb" ::: "memory");
-#endif
+    asm volatile(
+        "dsb ish\r\n"
+        "dsb ish\r\n"
+        "isb\r\n" ::: "memory");
 }
 
 void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {

src/core/arm/nce/interpreter_visitor.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
@@ -7,6 +7,8 @@
 
 #include <numeric>
 #include "core/arm/nce/interpreter_visitor.h"
+#include "core/memory.h"
+#include "dynarmic/common/context.h"
 
 namespace Core {
 
@@ -59,7 +61,7 @@ static u64 SignExtend(u64 value, u64 bitsize, u64 regsize) {
     if (regsize == 64) {
         return SignExtendToLong(value, bitsize);
     } else {
-        return SignExtendToWord(static_cast<u32>(value), bitsize);
+        return SignExtendToWord(u32(value), bitsize);
     }
 }
 
@@ -147,11 +149,11 @@ u64 InterpreterVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shi
 }
 
 u128 InterpreterVisitor::GetVec(Vec v) {
-    return m_fpsimd_regs[static_cast<u32>(v)];
+    return m_fpsimd_regs[u32(v)];
 }
 
 u64 InterpreterVisitor::GetReg(Reg r) {
-    return m_regs[static_cast<u32>(r)];
+    return m_regs[u32(r)];
 }
 
 u64 InterpreterVisitor::GetSp() {
@@ -163,11 +165,11 @@ u64 InterpreterVisitor::GetPc() {
 }
 
 void InterpreterVisitor::SetVec(Vec v, u128 value) {
-    m_fpsimd_regs[static_cast<u32>(v)] = value;
+    m_fpsimd_regs[u32(v)] = value;
 }
 
 void InterpreterVisitor::SetReg(Reg r, u64 value) {
-    m_regs[static_cast<u32>(r)] = value;
+    m_regs[u32(r)] = value;
 }
 
 void InterpreterVisitor::SetSp(u64 value) {
@@ -674,7 +676,7 @@ bool InterpreterVisitor::STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> opti
                                   Reg Rt) {
     const Imm<1> opc_0{0};
     const size_t scale = size.ZeroExtend<size_t>();
-    const u8 shift = S ? static_cast<u8>(scale) : 0;
+    const u8 shift = S ? u8(scale) : 0;
     if (!option.Bit<1>()) {
         // Unallocated encoding
         return false;
@@ -686,7 +688,7 @@ bool InterpreterVisitor::LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> opti
                                   Reg Rt) {
     const Imm<1> opc_0{1};
     const size_t scale = size.ZeroExtend<size_t>();
-    const u8 shift = S ? static_cast<u8>(scale) : 0;
+    const u8 shift = S ? u8(scale) : 0;
     if (!option.Bit<1>()) {
         // Unallocated encoding
         return false;
@@ -737,7 +739,7 @@ bool InterpreterVisitor::STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
         // Unallocated encoding
         return false;
     }
-    const u8 shift = S ? static_cast<u8>(scale) : 0;
+    const u8 shift = S ? u8(scale) : 0;
     if (!option.Bit<1>()) {
         // Unallocated encoding
         return false;
@@ -753,7 +755,7 @@ bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
         // Unallocated encoding
         return false;
     }
-    const u8 shift = S ? static_cast<u8>(scale) : 0;
+    const u8 shift = S ? u8(scale) : 0;
     if (!option.Bit<1>()) {
         // Unallocated encoding
         return false;
@@ -761,24 +763,25 @@ bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
     return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
 }
 
-std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
-                                                 fpsimd_context* fpsimd_context) {
-    std::span<u64, 31> regs(reinterpret_cast<u64*>(context->regs), 31);
-    std::span<u128, 32> vregs(reinterpret_cast<u128*>(fpsimd_context->vregs), 32);
-    u64& sp = *reinterpret_cast<u64*>(&context->sp);
-    const u64& pc = *reinterpret_cast<u64*>(&context->pc);
+std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context) {
+    CTX_DECLARE(raw_context);
+    std::span<u64, 31> regs(reinterpret_cast<u64*>(&CTX_X(0)), 31);
+    std::span<u128, 32> vregs(reinterpret_cast<u128*>(&CTX_Q(0)), 32);
 
-    InterpreterVisitor visitor(memory, regs, vregs, sp, pc);
-    u32 instruction = memory.Read32(pc);
+    // Store temporal to not break aliasing rules :)
+    u64 tmp_sp = CTX_SP;
+    u64 tmp_pc = CTX_PC;
+    u32 instruction = memory.Read32(tmp_pc);
     bool was_executed = false;
-
+    InterpreterVisitor visitor(memory, regs, vregs, tmp_sp, tmp_pc);
     if (auto decoder = Dynarmic::A64::Decode<VisitorBase>(instruction)) {
         was_executed = decoder->get().call(visitor, instruction);
     } else {
         LOG_ERROR(Core_ARM, "Unallocated encoding: {:#x}", instruction);
     }
-
-    return was_executed ? std::optional<u64>(pc + 4) : std::nullopt;
+    CTX_SP = tmp_sp;
+    CTX_PC = tmp_pc;
+    return was_executed ? std::optional<u64>(tmp_pc + 4) : std::nullopt;
 }
 
 } // namespace Core

src/core/arm/nce/interpreter_visitor.h

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
@@ -105,7 +105,6 @@ private:
     const u64& m_pc;
 };
 
-std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
-                                                 fpsimd_context* fpsimd_context);
+std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context);
 
 } // namespace Core

src/dynarmic/src/dynarmic/CMakeLists.txt

@@ -105,6 +105,9 @@ add_library(dynarmic STATIC
     frontend/A32/decoder/thumb32.inc
     frontend/A32/decoder/vfp.h
     frontend/A32/decoder/vfp.inc
+    frontend/A32/disassembler/disassembler.h
+    frontend/A32/disassembler/disassembler_arm.cpp
+    frontend/A32/disassembler/disassembler_thumb.cpp
     frontend/A32/FPSCR.h
     frontend/A32/ITState.h
     frontend/A32/PSR.h
@@ -119,6 +122,7 @@ add_library(dynarmic STATIC
     interface/A32/config.h
     interface/A32/coprocessor.h
     interface/A32/coprocessor_util.h
+    interface/A32/disassembler.h
     # A64
     frontend/A64/a64_ir_emitter.cpp
     frontend/A64/a64_ir_emitter.h

src/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h

@@ -0,0 +1,20 @@
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#pragma once
+
+#include <string>
+
+#include "dynarmic/common/common_types.h"
+
+namespace Dynarmic::A32 {
+
+std::string DisassembleArm(u32 instruction);
+std::string DisassembleThumb16(u16 instruction);
+
+}  // namespace Dynarmic::A32

src/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp

@@ -0,0 +1,397 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include <cstdlib>
+#include <string>
+
+#include <fmt/format.h>
+#include <fmt/ostream.h>
+#include <mcl/bit/bit_field.hpp>
+
+#include "dynarmic/common/string_util.h"
+#include "dynarmic/frontend/A32/a32_types.h"
+#include "dynarmic/frontend/A32/decoder/thumb16.h"
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
+#include "dynarmic/frontend/imm.h"
+
+namespace Dynarmic::A32 {
+
+class DisassemblerVisitor {
+public:
+    using instruction_return_type = std::string;
+
+    std::string thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) {
+        return fmt::format("lsls {}, {}, #{}", d, m, imm5.ZeroExtend());
+    }
+
+    std::string thumb16_LSR_imm(Imm<5> imm5, Reg m, Reg d) {
+        const u32 shift = imm5 != 0 ? imm5.ZeroExtend() : 32U;
+        return fmt::format("lsrs {}, {}, #{}", d, m, shift);
+    }
+
+    std::string thumb16_ASR_imm(Imm<5> imm5, Reg m, Reg d) {
+        const u32 shift = imm5 != 0 ? imm5.ZeroExtend() : 32U;
+        return fmt::format("asrs {}, {}, #{}", d, m, shift);
+    }
+
+    std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
+        return fmt::format("adds {}, {}, {}", d, n, m);
+    }
+
+    std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) {
+        return fmt::format("subs {}, {}, {}", d, n, m);
+    }
+
+    std::string thumb16_ADD_imm_t1(Imm<3> imm3, Reg n, Reg d) {
+        return fmt::format("adds {}, {}, #{}", d, n, imm3.ZeroExtend());
+    }
+
+    std::string thumb16_SUB_imm_t1(Imm<3> imm3, Reg n, Reg d) {
+        return fmt::format("subs {}, {}, #{}", d, n, imm3.ZeroExtend());
+    }
+
+    std::string thumb16_MOV_imm(Reg d, Imm<8> imm8) {
+        return fmt::format("movs {}, #{}", d, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_CMP_imm(Reg n, Imm<8> imm8) {
+        return fmt::format("cmp {}, #{}", n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_ADD_imm_t2(Reg d_n, Imm<8> imm8) {
+        return fmt::format("adds {}, #{}", d_n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_SUB_imm_t2(Reg d_n, Imm<8> imm8) {
+        return fmt::format("subs {}, #{}", d_n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_AND_reg(Reg m, Reg d_n) {
+        return fmt::format("ands {}, {}", d_n, m);
+    }
+
+    std::string thumb16_EOR_reg(Reg m, Reg d_n) {
+        return fmt::format("eors {}, {}", d_n, m);
+    }
+
+    std::string thumb16_LSL_reg(Reg m, Reg d_n) {
+        return fmt::format("lsls {}, {}", d_n, m);
+    }
+
+    std::string thumb16_LSR_reg(Reg m, Reg d_n) {
+        return fmt::format("lsrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ASR_reg(Reg m, Reg d_n) {
+        return fmt::format("asrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ADC_reg(Reg m, Reg d_n) {
+        return fmt::format("adcs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_SBC_reg(Reg m, Reg d_n) {
+        return fmt::format("sbcs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ROR_reg(Reg m, Reg d_n) {
+        return fmt::format("rors {}, {}", d_n, m);
+    }
+
+    std::string thumb16_TST_reg(Reg m, Reg n) {
+        return fmt::format("tst {}, {}", n, m);
+    }
+
+    std::string thumb16_RSB_imm(Reg n, Reg d) {
+        // Pre-UAL syntax: NEGS <Rd>, <Rn>
+        return fmt::format("rsbs {}, {}, #0", d, n);
+    }
+
+    std::string thumb16_CMP_reg_t1(Reg m, Reg n) {
+        return fmt::format("cmp {}, {}", n, m);
+    }
+
+    std::string thumb16_CMN_reg(Reg m, Reg n) {
+        return fmt::format("cmn {}, {}", n, m);
+    }
+
+    std::string thumb16_ORR_reg(Reg m, Reg d_n) {
+        return fmt::format("orrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_MUL_reg(Reg n, Reg d_m) {
+        return fmt::format("muls {}, {}, {}", d_m, n, d_m);
+    }
+
+    std::string thumb16_BIC_reg(Reg m, Reg d_n) {
+        return fmt::format("bics {}, {}", d_n, m);
+    }
+
+    std::string thumb16_MVN_reg(Reg m, Reg d) {
+        return fmt::format("mvns {}, {}", d, m);
+    }
+
+    std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
+        const Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
+        return fmt::format("add {}, {}", d_n, m);
+    }
+
+    std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
+        const Reg n = n_hi ? (n_lo + 8) : n_lo;
+        return fmt::format("cmp {}, {}", n, m);
+    }
+
+    std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
+        const Reg d = d_hi ? (d_lo + 8) : d_lo;
+        return fmt::format("mov {}, {}", d, m);
+    }
+
+    std::string thumb16_LDR_literal(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [pc, #{}]", t, imm32);
+    }
+
+    std::string thumb16_STR_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("str {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("strh {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("strb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrsb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldr {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrh {}, [%s, %s]", t, n, m);
+    }
+
+    std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrsh {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STR_imm_t1(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 2;
+        return fmt::format("str {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDR_imm_t1(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STRB_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend();
+        return fmt::format("strb {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDRB_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend();
+        return fmt::format("ldrb {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STRH_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 1;
+        return fmt::format("strh {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDRH_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 1;
+        return fmt::format("ldrh {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STR_imm_t2(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("str {}, [sp, #{}]", t, imm32);
+    }
+
+    std::string thumb16_LDR_imm_t2(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [sp, #{}]", t, imm32);
+    }
+
+    std::string thumb16_ADR(Reg d, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("adr {}, +#{}", d, imm32);
+    }
+
+    std::string thumb16_ADD_sp_t1(Reg d, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("add {}, sp, #{}", d, imm32);
+    }
+
+    std::string thumb16_ADD_sp_t2(Imm<7> imm7) {
+        const u32 imm32 = imm7.ZeroExtend() << 2;
+        return fmt::format("add sp, sp, #{}", imm32);
+    }
+
+    std::string thumb16_SUB_sp(Imm<7> imm7) {
+        const u32 imm32 = imm7.ZeroExtend() << 2;
+        return fmt::format("sub sp, sp, #{}", imm32);
+    }
+
+    std::string thumb16_NOP() {
+        return "nop";
+    }
+
+    std::string thumb16_SEV() {
+        return "sev";
+    }
+
+    std::string thumb16_SEVL() {
+        return "sevl";
+    }
+
+    std::string thumb16_WFE() {
+        return "wfe";
+    }
+
+    std::string thumb16_WFI() {
+        return "wfi";
+    }
+
+    std::string thumb16_YIELD() {
+        return "yield";
+    }
+
+    std::string thumb16_IT(Imm<8> imm8) {
+        const Cond firstcond = imm8.Bits<4, 7, Cond>();
+        const bool firstcond0 = imm8.Bit<4>();
+        const auto [x, y, z] = [&] {
+            if (imm8.Bits<0, 3>() == 0b1000) {
+                return std::make_tuple("", "", "");
+            }
+            if (imm8.Bits<0, 2>() == 0b100) {
+                return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", "", "");
+            }
+            if (imm8.Bits<0, 1>() == 0b10) {
+                return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", imm8.Bit<2>() == firstcond0 ? "t" : "e", "");
+            }
+            // Sanity note: Here imm8.Bit<0>() is guaranteed to be == 1. (imm8 can never be 0bxxxx0000)
+            return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", imm8.Bit<2>() == firstcond0 ? "t" : "e", imm8.Bit<1>() == firstcond0 ? "t" : "e");
+        }();
+        return fmt::format("it{}{}{} {}", x, y, z, CondToString(firstcond));
+    }
+
+    std::string thumb16_SXTH(Reg m, Reg d) {
+        return fmt::format("sxth {}, {}", d, m);
+    }
+
+    std::string thumb16_SXTB(Reg m, Reg d) {
+        return fmt::format("sxtb {}, {}", d, m);
+    }
+
+    std::string thumb16_UXTH(Reg m, Reg d) {
+        return fmt::format("uxth {}, {}", d, m);
+    }
+
+    std::string thumb16_UXTB(Reg m, Reg d) {
+        return fmt::format("uxtb {}, {}", d, m);
+    }
+
+    std::string thumb16_PUSH(bool M, RegList reg_list) {
+        if (M)
+            reg_list |= 1 << 14;
+        return fmt::format("push {{{}}}", RegListToString(reg_list));
+    }
+
+    std::string thumb16_POP(bool P, RegList reg_list) {
+        if (P)
+            reg_list |= 1 << 15;
+        return fmt::format("pop {{{}}}", RegListToString(reg_list));
+    }
+
+    std::string thumb16_SETEND(bool E) {
+        return fmt::format("setend {}", E ? "BE" : "LE");
+    }
+
+    std::string thumb16_CPS(bool im, bool a, bool i, bool f) {
+        return fmt::format("cps{} {}{}{}", im ? "id" : "ie", a ? "a" : "", i ? "i" : "", f ? "f" : "");
+    }
+
+    std::string thumb16_REV(Reg m, Reg d) {
+        return fmt::format("rev {}, {}", d, m);
+    }
+
+    std::string thumb16_REV16(Reg m, Reg d) {
+        return fmt::format("rev16 {}, {}", d, m);
+    }
+
+    std::string thumb16_REVSH(Reg m, Reg d) {
+        return fmt::format("revsh {}, {}", d, m);
+    }
+
+    std::string thumb16_BKPT(Imm<8> imm8) {
+        return fmt::format("bkpt #{}", imm8.ZeroExtend());
+    }
+
+    std::string thumb16_STMIA(Reg n, RegList reg_list) {
+        return fmt::format("stm {}!, {{{}}}", n, RegListToString(reg_list));
+    }
+
+    std::string thumb16_LDMIA(Reg n, RegList reg_list) {
+        const bool write_back = !mcl::bit::get_bit(static_cast<size_t>(n), reg_list);
+        return fmt::format("ldm {}{}, {{{}}}", n, write_back ? "!" : "", RegListToString(reg_list));
+    }
+
+    std::string thumb16_BX(Reg m) {
+        return fmt::format("bx {}", m);
+    }
+
+    std::string thumb16_BLX_reg(Reg m) {
+        return fmt::format("blx {}", m);
+    }
+
+    std::string thumb16_CBZ_CBNZ(bool nonzero, Imm<1> i, Imm<5> imm5, Reg n) {
+        const char* const name = nonzero ? "cbnz" : "cbz";
+        const u32 imm = concatenate(i, imm5, Imm<1>{0}).ZeroExtend();
+
+        return fmt::format("{} {}, #{}", name, n, imm);
+    }
+
+    std::string thumb16_UDF() {
+        return fmt::format("udf");
+    }
+
+    std::string thumb16_SVC(Imm<8> imm8) {
+        return fmt::format("svc #{}", imm8.ZeroExtend());
+    }
+
+    std::string thumb16_B_t1(Cond cond, Imm<8> imm8) {
+        const s32 imm32 = static_cast<s32>((imm8.SignExtend<u32>() << 1) + 4);
+        return fmt::format("b{} {}#{}",
+                           CondToString(cond),
+                           Common::SignToChar(imm32),
+                           abs(imm32));
+    }
+
+    std::string thumb16_B_t2(Imm<11> imm11) {
+        const s32 imm32 = static_cast<s32>((imm11.SignExtend<u32>() << 1) + 4);
+        return fmt::format("b {}#{}",
+                           Common::SignToChar(imm32),
+                           abs(imm32));
+    }
+};
+
+std::string DisassembleThumb16(u16 instruction) {
+    DisassemblerVisitor visitor;
+    auto decoder = DecodeThumb16<DisassemblerVisitor>(instruction);
+    return !decoder ? fmt::format("UNKNOWN: {:x}", instruction) : decoder->get().call(visitor, instruction);
+}
+
+}  // namespace Dynarmic::A32

src/dynarmic/src/dynarmic/interface/A32/disassembler.h

@@ -0,0 +1,18 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#pragma once
+
+#include <cstdint>
+#include <string>
+
+namespace Dynarmic {
+namespace A32 {
+
+std::string DisassembleArm(std::uint32_t instruction);
+std::string DisassembleThumb16(std::uint16_t instruction);
+
+}  // namespace A32
+}  // namespace Dynarmic

src/dynarmic/tests/A32/fuzz_thumb.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -26,6 +26,7 @@
 #include "dynarmic/frontend/A32/FPSCR.h"
 #include "dynarmic/frontend/A32/PSR.h"
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
 #include "dynarmic/frontend/A32/translate/a32_translate.h"
 #include "dynarmic/interface/A32/a32.h"
 #include "dynarmic/ir/basic_block.h"

src/dynarmic/tests/A32/test_arm_disassembler.cpp

@@ -0,0 +1,381 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include <catch2/catch_test_macros.hpp>
+
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
+
+using Dynarmic::A32::DisassembleArm;
+
+TEST_CASE("Disassemble branch instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xEAFFFFFE) == "b +#0");
+    REQUIRE(DisassembleArm(0xEB000008) == "bl +#40");
+    REQUIRE(DisassembleArm(0xFBFFFFFE) == "blx +#2");
+    REQUIRE(DisassembleArm(0xFAFFFFFF) == "blx +#4");
+    REQUIRE(DisassembleArm(0xFBE1E7FE) == "blx -#7888894");
+    REQUIRE(DisassembleArm(0xE12FFF3D) == "blx sp");
+    REQUIRE(DisassembleArm(0x312FFF13) == "bxcc r3");
+    REQUIRE(DisassembleArm(0x012FFF29) == "bxjeq r9");
+}
+
+TEST_CASE("Disassemble data processing instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE2A21004) == "adc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0A21143) == "adc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0A21103) == "adc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0A21123) == "adc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0A21163) == "adc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0A21003) == "adc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0A21063) == "adc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0A21453) == "adc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0A21413) == "adc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0A21433) == "adc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0A21473) == "adc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2B21004) == "adcs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0B21143) == "adcs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0B21103) == "adcs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0B21123) == "adcs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0B21163) == "adcs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0B21003) == "adcs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0B21063) == "adcs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0B21453) == "adcs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0B21413) == "adcs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0B21433) == "adcs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0B21473) == "adcs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2853004) == "add r3, r5, #4");
+    REQUIRE(DisassembleArm(0xE0821143) == "add r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0821103) == "add r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0821123) == "add r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0821163) == "add r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0821003) == "add r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0821453) == "add r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0821413) == "add r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0821433) == "add r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0821473) == "add r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0821063) == "add r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2953004) == "adds r3, r5, #4");
+    REQUIRE(DisassembleArm(0xE0921143) == "adds r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0921103) == "adds r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0921123) == "adds r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0921163) == "adds r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0921003) == "adds r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0921063) == "adds r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0921453) == "adds r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0921413) == "adds r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0921433) == "adds r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0921473) == "adds r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2021004) == "and r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0021143) == "and r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0021103) == "and r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0021123) == "and r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0021163) == "and r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0021003) == "and r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0021453) == "and r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0021413) == "and r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0021433) == "and r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0021473) == "and r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0021063) == "and r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2121004) == "ands r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0121143) == "ands r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0121103) == "ands r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0121123) == "ands r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0121163) == "ands r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0121003) == "ands r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0121063) == "ands r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0121453) == "ands r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0121413) == "ands r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0121433) == "ands r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0121473) == "ands r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3C21004) == "bic r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1C21143) == "bic r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1C21103) == "bic r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1C21123) == "bic r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1C21163) == "bic r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1C21003) == "bic r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1C21453) == "bic r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1C21413) == "bic r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1C21433) == "bic r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1C21473) == "bic r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE1C21063) == "bic r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE3D21004) == "bics r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1D21143) == "bics r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1D21103) == "bics r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1D21123) == "bics r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1D21163) == "bics r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1D21003) == "bics r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1D21063) == "bics r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1D21453) == "bics r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1D21413) == "bics r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1D21433) == "bics r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1D21473) == "bics r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3710004) == "cmn r1, #4");
+    REQUIRE(DisassembleArm(0xE1710142) == "cmn r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1710102) == "cmn r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1710122) == "cmn r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1710162) == "cmn r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1710002) == "cmn r1, r2");
+    REQUIRE(DisassembleArm(0xE1710062) == "cmn r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1710352) == "cmn r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1710312) == "cmn r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1710332) == "cmn r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1710372) == "cmn r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3510004) == "cmp r1, #4");
+    REQUIRE(DisassembleArm(0xE1510142) == "cmp r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1510102) == "cmp r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1510122) == "cmp r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1510162) == "cmp r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1510002) == "cmp r1, r2");
+    REQUIRE(DisassembleArm(0xE1510062) == "cmp r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1510352) == "cmp r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1510312) == "cmp r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1510332) == "cmp r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1510372) == "cmp r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE2221004) == "eor r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0221243) == "eor r1, r2, r3, asr #4");
+    REQUIRE(DisassembleArm(0xE0221203) == "eor r1, r2, r3, lsl #4");
+    REQUIRE(DisassembleArm(0xE0221223) == "eor r1, r2, r3, lsr #4");
+    REQUIRE(DisassembleArm(0xE0221263) == "eor r1, r2, r3, ror #4");
+    REQUIRE(DisassembleArm(0xE0221003) == "eor r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0221453) == "eor r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0221413) == "eor r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0221433) == "eor r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0221473) == "eor r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0221063) == "eor r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2321004) == "eors r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0321243) == "eors r1, r2, r3, asr #4");
+    REQUIRE(DisassembleArm(0xE0321203) == "eors r1, r2, r3, lsl #4");
+    REQUIRE(DisassembleArm(0xE0321223) == "eors r1, r2, r3, lsr #4");
+    REQUIRE(DisassembleArm(0xE0321263) == "eors r1, r2, r3, ror #4");
+    REQUIRE(DisassembleArm(0xE0321003) == "eors r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0321453) == "eors r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0321413) == "eors r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0321433) == "eors r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0321473) == "eors r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0321063) == "eors r1, r2, r3, rrx");
+
+    REQUIRE(DisassembleArm(0xE3A010FF) == "mov r1, #255");
+    REQUIRE(DisassembleArm(0xE1A01142) == "mov r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1A01102) == "mov r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1A01122) == "mov r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1A01162) == "mov r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1A01062) == "mov r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1A0E00F) == "mov lr, pc");
+    REQUIRE(DisassembleArm(0xE3B010FF) == "movs r1, #255");
+    REQUIRE(DisassembleArm(0xE1B0E00F) == "movs lr, pc");
+    REQUIRE(DisassembleArm(0xE1B01142) == "movs r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1B01102) == "movs r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1B01122) == "movs r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1B01162) == "movs r1, r2, ror #2");
+
+    REQUIRE(DisassembleArm(0xE3E01004) == "mvn r1, #4");
+    REQUIRE(DisassembleArm(0xE1E01142) == "mvn r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1E01102) == "mvn r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1E01122) == "mvn r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1E01162) == "mvn r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1E01062) == "mvn r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1E01002) == "mvn r1, r2");
+    REQUIRE(DisassembleArm(0xE1E01352) == "mvn r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1E01312) == "mvn r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1E01332) == "mvn r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1E01372) == "mvn r1, r2, ror r3");
+    REQUIRE(DisassembleArm(0xE3F01004) == "mvns r1, #4");
+    REQUIRE(DisassembleArm(0xE1F01142) == "mvns r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1F01102) == "mvns r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1F01122) == "mvns r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1F01162) == "mvns r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1F01062) == "mvns r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1F01002) == "mvns r1, r2");
+    REQUIRE(DisassembleArm(0xE1F01352) == "mvns r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1F01312) == "mvns r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1F01332) == "mvns r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1F01372) == "mvns r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3821004) == "orr r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1821143) == "orr r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1821103) == "orr r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1821123) == "orr r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1821163) == "orr r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1821063) == "orr r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1821003) == "orr r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1821453) == "orr r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1821413) == "orr r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1821433) == "orr r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1821473) == "orr r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE3921004) == "orrs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1921143) == "orrs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1921103) == "orrs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1921123) == "orrs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1921163) == "orrs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1921063) == "orrs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1921003) == "orrs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1921453) == "orrs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1921413) == "orrs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1921433) == "orrs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1921473) == "orrs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2621004) == "rsb r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0621143) == "rsb r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0621103) == "rsb r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0621123) == "rsb r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0621163) == "rsb r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0621063) == "rsb r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0621003) == "rsb r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0621453) == "rsb r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0621413) == "rsb r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0621433) == "rsb r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0621473) == "rsb r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2721004) == "rsbs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0721143) == "rsbs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0721103) == "rsbs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0721123) == "rsbs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0721163) == "rsbs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0721063) == "rsbs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0721003) == "rsbs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0721453) == "rsbs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0721413) == "rsbs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0721433) == "rsbs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0721473) == "rsbs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2E21004) == "rsc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0E21143) == "rsc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0E21103) == "rsc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0E21123) == "rsc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0E21163) == "rsc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0E21063) == "rsc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0E21003) == "rsc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0E21453) == "rsc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0E21413) == "rsc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0E21433) == "rsc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0E21473) == "rsc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2F21004) == "rscs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0F21143) == "rscs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0F21103) == "rscs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0F21123) == "rscs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0F21163) == "rscs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0F21063) == "rscs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0F21003) == "rscs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0F21453) == "rscs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0F21413) == "rscs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0F21433) == "rscs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0F21473) == "rscs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2C21004) == "sbc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0C21143) == "sbc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0C21103) == "sbc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0C21123) == "sbc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0C21163) == "sbc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0C21063) == "sbc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0C21003) == "sbc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0C21453) == "sbc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0C21413) == "sbc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0C21433) == "sbc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0C21473) == "sbc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2D21004) == "sbcs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0D21143) == "sbcs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0D21103) == "sbcs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0D21123) == "sbcs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0D21163) == "sbcs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0D21063) == "sbcs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0D21003) == "sbcs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0D21453) == "sbcs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0D21413) == "sbcs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0D21433) == "sbcs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0D21473) == "sbcs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3310004) == "teq r1, #4");
+    REQUIRE(DisassembleArm(0xE1310142) == "teq r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1310102) == "teq r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1310122) == "teq r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1310162) == "teq r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1310002) == "teq r1, r2");
+    REQUIRE(DisassembleArm(0xE1310062) == "teq r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1310352) == "teq r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1310312) == "teq r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1310332) == "teq r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1310372) == "teq r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3110004) == "tst r1, #4");
+    REQUIRE(DisassembleArm(0xE1110142) == "tst r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1110102) == "tst r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1110122) == "tst r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1110162) == "tst r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1110002) == "tst r1, r2");
+    REQUIRE(DisassembleArm(0xE1110062) == "tst r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1110352) == "tst r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1110312) == "tst r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1110332) == "tst r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1110372) == "tst r1, r2, ror r3");
+}
+
+TEST_CASE("Disassemble half-word multiply and multiply accumulate instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE1003281) == "smlabb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032C1) == "smlabt r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032A1) == "smlatb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032E1) == "smlatt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE1203281) == "smlawb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE12032C1) == "smlawt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE12002A1) == "smulwb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE12002E1) == "smulwt r0, r1, r2");
+
+    REQUIRE(DisassembleArm(0xE1410382) == "smlalbb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103C2) == "smlalbt r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103A2) == "smlaltb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103E2) == "smlaltt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE1600281) == "smulbb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002C1) == "smulbt r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002A1) == "smultb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002E1) == "smultt r0, r1, r2");
+}
+
+TEST_CASE("Disassemble multiply and multiply accumulate instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE0214392) == "mla r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0314392) == "mlas r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0010392) == "mul r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0110392) == "muls r1, r2, r3");
+
+    // TODO: MLS should be here whenever it's supported.
+
+    REQUIRE(DisassembleArm(0xE0E21493) == "smlal r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0F21493) == "smlals r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0C21493) == "smull r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0D21493) == "smulls r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0421493) == "umaal r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0A21493) == "umlal r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0B21493) == "umlals r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0821493) == "umull r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0921493) == "umulls r1, r2, r3, r4");
+}
+
+TEST_CASE("Disassemble synchronization primitive instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE1921F9F) == "ldrex r1, [r2]");
+    REQUIRE(DisassembleArm(0xE1D21F9F) == "ldrexb r1, [r2]");
+    REQUIRE(DisassembleArm(0xE1B31F9F) == "ldrexd r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1F21F9F) == "ldrexh r1, [r2]");
+
+    REQUIRE(DisassembleArm(0xE1831F92) == "strex r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1C31F92) == "strexb r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1A41F92) == "strexd r1, r2, r3, [r4]");
+    REQUIRE(DisassembleArm(0xE1E31F92) == "strexh r1, r2, [r3]");
+
+    REQUIRE(DisassembleArm(0xE1031092) == "swp r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1431092) == "swpb r1, r2, [r3]");
+}
+
+TEST_CASE("Disassemble load / store multiple instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE92D500F) == "stmdb sp!, {r0, r1, r2, r3, r12, lr}");
+}

src/dynarmic/tests/CMakeLists.txt

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+# SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 # SPDX-License-Identifier: GPL-3.0-or-later
 include(TargetArchitectureSpecificSources)
 
@@ -9,6 +9,7 @@ add_executable(dynarmic_tests
     fp/unpacked_tests.cpp
     rand_int.h
     # A32
+    A32/test_arm_disassembler.cpp
     A32/test_arm_instructions.cpp
     A32/test_coprocessor.cpp
     A32/test_svc.cpp

src/dynarmic/tests/print_info.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -34,6 +34,7 @@
 #include "dynarmic/frontend/A64/translate/impl/impl.h"
 #include "dynarmic/interface/A32/a32.h"
 #include "dynarmic/interface/A32/config.h"
+#include "dynarmic/interface/A32/disassembler.h"
 #include "dynarmic/ir/basic_block.h"
 #include "dynarmic/ir/opt_passes.h"