[vulkan] Improve frame pacing (#3535)

This improves frame pacing control, fixes accumulated drift, and adds the ability to change it while the game is running.

Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3535
Co-authored-by: MaranBr <maranbr@outlook.com>
Co-committed-by: MaranBr <maranbr@outlook.com>

CMakeModules/GenerateSCMRev.cmake

@@ -37,7 +37,7 @@ set(GIT_DESC ${BUILD_VERSION})
 
 # Auto-updater metadata! Must somewhat mirror GitHub API endpoint
 set(BUILD_AUTO_UPDATE_WEBSITE "https://github.com")
-set(BUILD_AUTO_UPDATE_API "http://api.github.com")
+set(BUILD_AUTO_UPDATE_API "https://api.github.com")
 
 if (NIGHTLY_BUILD)
     set(BUILD_AUTO_UPDATE_REPO "Eden-CI/Nightly")

docs/user/Native.md

@@ -6,7 +6,4 @@ Debugging on physical hardware can get tedious and time consuming. Users are emp
 
 **Standard key prefix**: Allows to redirect the key manager to a file other than `prod.keys` (for example `other` would redirect to `other.keys`). This is useful for testing multiple keysets. Default is `prod`.
 
-**Changing serial**: Very basic way to set debug values for the serial (and battery number). Developers do not need to write the full serial as it will be writen in-place (that is, it will be filled with the default serial and then overwrite the serial from the beginning).
-- Battery serial: `YUZU0EMULATOR14022024`
-- Board serial: `YUZ10000000001`
-If the user were to set their board serial as `ABC`, then it will be written in-place and the resulting serial would be `ABC10000000001`. There are no underlying checks to ensure correctness of serials other than a hard limit of 16-characters for both.
+**Changing serial**: Very basic way to set debug values for the serial (and battery number). Developers do not need to write the full serial as only the first digits (excluding the last) will be accoutned for. Region settings will affect the generated serial. The serial corresponds to a non-OLED/Lite console.

src/android/app/src/main/res/values/arrays.xml

@@ -534,8 +534,8 @@
         <item>@string/frame_pacing_mode_target_Auto</item>
         <item>@string/frame_pacing_mode_target_30</item>
         <item>@string/frame_pacing_mode_target_60</item>
+        <item>@string/frame_pacing_mode_target_90</item>
         <item>@string/frame_pacing_mode_target_120</item>
-        <item>@string/frame_pacing_mode_target_240</item>
     </string-array>
     <integer-array name="framePacingModeValues">
         <item>0</item>

src/android/app/src/main/res/values/strings.xml

@@ -1038,8 +1038,8 @@
     <string name="frame_pacing_mode_target_Auto">Auto</string>
     <string name="frame_pacing_mode_target_30">30 FPS</string>
     <string name="frame_pacing_mode_target_60">60 FPS</string>
+    <string name="frame_pacing_mode_target_90">90 FPS</string>
     <string name="frame_pacing_mode_target_120">120 FPS</string>
-    <string name="frame_pacing_mode_target_240">240 FPS</string>
 
     <!-- ASTC Decoding Method Choices -->
     <string name="accelerate_astc_cpu" translatable="false">CPU</string>

src/common/settings.h

@@ -462,9 +462,12 @@ struct Values {
     SwitchableSetting<FramePacingMode, true> frame_pacing_mode{linkage,
                                                                FramePacingMode::Target_Auto,
                                                                FramePacingMode::Target_Auto,
-                                                               FramePacingMode::Target_240,
+                                                               FramePacingMode::Target_120,
                                                                "frame_pacing_mode",
-                                                               Category::RendererAdvanced};
+                                                               Category::RendererAdvanced,
+                                                               Specialization::Default,
+                                                               true,
+                                                               true};
 
     SwitchableSetting<AstcRecompression, true> astc_recompression{linkage,
                                                                   AstcRecompression::Uncompressed,
@@ -620,11 +623,11 @@ struct Values {
                                                      "language_index",
                                                      Category::System};
     SwitchableSetting<Region, true> region_index{linkage, Region::Usa, "region_index", Category::System};
-    SwitchableSetting<TimeZone, true> time_zone_index{linkage, TimeZone::Auto,
-                                                      "time_zone_index", Category::System};
+    SwitchableSetting<TimeZone, true> time_zone_index{linkage, TimeZone::Auto, "time_zone_index", Category::System};
+    Setting<u32> serial_battery{linkage, 0, "serial_battery", Category::System};
+    Setting<u32> serial_unit{linkage, 0, "serial_unit", Category::System};
     // Measured in seconds since epoch
-    SwitchableSetting<bool> custom_rtc_enabled{
-                                               linkage, false, "custom_rtc_enabled", Category::System, Specialization::Paired, true, true};
+    SwitchableSetting<bool> custom_rtc_enabled{linkage, false, "custom_rtc_enabled", Category::System, Specialization::Paired, true, true};
     SwitchableSetting<s64> custom_rtc{
                                       linkage, 0,    "custom_rtc",       Category::System, Specialization::Time,
                                       false,   true, &custom_rtc_enabled};
@@ -794,8 +797,6 @@ struct Values {
                                            true};
 
     // Miscellaneous
-    Setting<std::string> serial_battery{linkage, std::string(), "serial_battery", Category::Miscellaneous};
-    Setting<std::string> serial_unit{linkage, std::string(), "serial_unit", Category::Miscellaneous};
     Setting<std::string> log_filter{linkage, "*:Info", "log_filter", Category::Miscellaneous};
     Setting<bool> log_flush_line{linkage, false, "flush_line", Category::Miscellaneous, Specialization::Default, true, true};
     Setting<bool> censor_username{linkage, true, "censor_username", Category::Miscellaneous};

src/common/settings_enums.h

@@ -129,7 +129,7 @@ ENUM(TimeZone, Auto, Default, Cet, Cst6Cdt, Cuba, Eet, Egypt, Eire, Est, Est5Edt
 ENUM(AnisotropyMode, Automatic, Default, X2, X4, X8, X16, X32, X64, None);
 ENUM(AstcDecodeMode, Cpu, Gpu, CpuAsynchronous);
 ENUM(AstcRecompression, Uncompressed, Bc1, Bc3);
-ENUM(FramePacingMode, Target_Auto, Target_30, Target_60, Target_120, Target_240);
+ENUM(FramePacingMode, Target_Auto, Target_30, Target_60, Target_90, Target_120);
 ENUM(VSyncMode, Immediate, Mailbox, Fifo, FifoRelaxed);
 ENUM(VramUsageMode, Conservative, Aggressive);
 ENUM(RendererBackend, OpenGL_GLSL, Vulkan, Null, OpenGL_GLASM, OpenGL_SPIRV);

src/core/core_timing.cpp

@@ -13,6 +13,11 @@
 #include "common/windows/timer_resolution.h"
 #endif
 
+#if defined(_WIN32) && defined(ARCHITECTURE_x86_64) && defined(__MINGW64__)
+#include "common/x64/cpu_detect.h"
+#include "common/x64/rdtsc.h"
+#endif
+
 #include "common/settings.h"
 #include "core/core_timing.h"
 #include "core/hardware_properties.h"
@@ -282,8 +287,45 @@ void CoreTiming::ThreadLoop() {
             const auto next_time = Advance();
             if (next_time) {
                 // There are more events left in the queue, wait until the next event.
-                auto wait_time = *next_time - GetGlobalTimeNs().count();
-                event.WaitFor(std::chrono::nanoseconds(wait_time));
+                if (auto wait_time = *next_time - GetGlobalTimeNs().count(); wait_time > 0) {
+#if defined(_WIN32) && defined(ARCHITECTURE_x86_64) && defined(__MINGW64__)
+                    while (!paused && !event.IsSet() && wait_time > 0) {
+                        wait_time = *next_time - GetGlobalTimeNs().count();
+                        if (wait_time >= timer_resolution_ns) {
+                            Common::Windows::SleepForOneTick();
+                        } else {
+                            // 100,000 cycles is a reasonable amount of time to wait to save on CPU resources.
+                            // For reference:
+                            // At 1 GHz, 100K cycles is 100us
+                            // At 2 GHz, 100K cycles is 50us
+                            // At 4 GHz, 100K cycles is 25us
+                            constexpr auto PauseCycles = 100'000U;
+                            auto const& caps = Common::GetCPUCaps();
+                            if (caps.waitpkg) {
+                                static constexpr auto RequestC02State = 0U;
+                                const auto tsc = Common::X64::FencedRDTSC() + PauseCycles;
+                                const auto eax = u32(tsc & 0xFFFFFFFF);
+                                const auto edx = u32(tsc >> 32);
+                                asm volatile("tpause %0" : : "r"(RequestC02State), "d"(edx), "a"(eax));
+                            } else if (caps.monitorx) {
+                                static constexpr auto EnableWaitTimeFlag = 1U << 1;
+                                static constexpr auto RequestC1State = 0U;
+                                // monitor_var should be aligned to a cache line.
+                                alignas(64) u64 monitor_var{};
+                                asm volatile("monitorx" : : "a"(&monitor_var), "c"(0), "d"(0));
+                                asm volatile("mwaitx" : : "a"(RequestC1State), "b"(PauseCycles), "c"(EnableWaitTimeFlag));
+                            } else {
+                                std::this_thread::yield();
+                            }
+                        }
+                    }
+                    if (event.IsSet()) {
+                        event.Reset();
+                    }
+#else
+                    event.WaitFor(std::chrono::nanoseconds(wait_time));
+#endif
+                }
             } else {
                 // Queue is empty, wait until another event is scheduled and signals us to
                 // continue.

src/core/hle/service/set/system_settings_server.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
@@ -980,25 +980,82 @@ Result ISystemSettingsServer::SetPrimaryAlbumStorage(PrimaryAlbumStorage primary
     R_SUCCEED();
 }
 
+static void Fill3DS_CRC(u32 d, char* data) {
+    std::array<u8, 10> digits = {
+        u8((d / 1000000000) % 100),
+        u8((d / 100000000) % 10),
+        u8((d / 10000000) % 10),
+        u8((d / 1000000) % 10),
+        u8((d / 100000) % 10),
+        u8((d / 10000) % 10),
+        u8((d / 1000) % 10),
+        u8((d / 100) % 10),
+        u8((d / 10) % 10),
+        u8(d % 10),
+    };
+    // Normalize to retail values
+    std::array<u8, 4> retail_digits = { 1, 4, 5, 7 };
+    digits[0] = retail_digits[(d % 10) % 4];
+    digits[1] = 0;
+    //
+    for (size_t i = 0; i < sizeof(digits); ++i)
+        data[i] = char(digits[i] + '0');
+    u8 sum_odd = 0, sum_even = 0;
+    for (size_t i = 0; i < sizeof(digits); i += 2) {
+        sum_odd += digits[i + 0];
+        sum_even += digits[i + 1];
+    }
+    u8 sum_digit = u8(((sum_even * 3) + sum_odd) % 10);
+    if (sum_digit != 0)
+        sum_digit = 10 - sum_digit;
+    data[sizeof(digits)] = char(sum_digit + '0');
+}
+
 Result ISystemSettingsServer::GetBatteryLot(Out<BatteryLot> out_battery_lot) {
     LOG_INFO(Service_SET, "called");
-    *out_battery_lot = {"YUZU0EMULATOR14022024"};
-    if (auto const s = ::Settings::values.serial_battery.GetValue(); !s.empty()) {
-        auto const max_size = out_battery_lot->lot_number.size();
-        auto const end = s.size() > max_size ? s.begin() + max_size : s.end();
-        std::copy(s.begin(), end, out_battery_lot->lot_number.begin());
-    }
+    *out_battery_lot = []{
+        u32 d = ::Settings::values.serial_battery.GetValue();
+        BatteryLot c{};
+        c.lot_number[0] = 'B';
+        c.lot_number[1] = 'H';
+        c.lot_number[2] = 'A';
+        c.lot_number[3] = 'C';
+        // TODO: I have no fucking idea what the letters mean
+        c.lot_number[4] = 'H';
+        c.lot_number[5] = 'Z';
+        c.lot_number[6] = 'Z';
+        c.lot_number[7] = 'A';
+        c.lot_number[8] = 'D';
+        c.lot_number[9] = char(((d / 100000) % 26) + 'A');
+        Fill3DS_CRC(d, c.lot_number.data() + 10);
+        return c;
+    }();
     R_SUCCEED();
 }
 
 Result ISystemSettingsServer::GetSerialNumber(Out<SerialNumber> out_console_serial) {
     LOG_INFO(Service_SET, "called");
-    *out_console_serial = {"YUZ10000000001"};
-    if (auto const s = ::Settings::values.serial_unit.GetValue(); !s.empty()) {
-        auto const max_size = out_console_serial->serial_number.size();
-        auto const end = s.size() > max_size ? s.begin() + max_size : s.end();
-        std::copy(s.begin(), end, out_console_serial->serial_number.begin());
-    }
+    *out_console_serial = []{
+        u32 d = ::Settings::values.serial_unit.GetValue();
+        SerialNumber c{};
+        c.serial_number[0] = 'X';
+        c.serial_number[1] = 'A';
+        c.serial_number[2] = [] {
+            // Adding another setting would be tedious so... let's just reuse region_index :)
+            switch (::Settings::values.region_index.GetValue()) {
+            case ::Settings::Region::Japan: return 'J';
+            case ::Settings::Region::Usa: return 'W';
+            case ::Settings::Region::Europe: return 'E';
+            case ::Settings::Region::Australia: return 'M'; //pretend its Malaysia
+            case ::Settings::Region::China:
+            case ::Settings::Region::Taiwan: return 'C';
+            case ::Settings::Region::Korea: return 'K';
+            default: return 'W';
+            }
+        }();
+        Fill3DS_CRC(d, c.serial_number.data() + 3);
+        return c;
+    }();
     R_SUCCEED();
 }
 

src/core/hle/service/spl/spl_module.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
@@ -178,7 +178,7 @@ void LoopProcess(Core::System& system) {
     auto module = std::make_shared<Module>();
 
     server_manager->RegisterNamedService("csrng", std::make_shared<CSRNG>(system, module));
-    server_manager->RegisterNamedService("spl", std::make_shared<SPL>(system, module));
+    server_manager->RegisterNamedService("spl:", std::make_shared<SPL>(system, module));
     server_manager->RegisterNamedService("spl:mig", std::make_shared<SPL_MIG>(system, module));
     server_manager->RegisterNamedService("spl:fs", std::make_shared<SPL_FS>(system, module));
     server_manager->RegisterNamedService("spl:ssl", std::make_shared<SPL_SSL>(system, module));

src/dynarmic/src/dynarmic/CMakeLists.txt

@@ -105,6 +105,9 @@ add_library(dynarmic STATIC
     frontend/A32/decoder/thumb32.inc
     frontend/A32/decoder/vfp.h
     frontend/A32/decoder/vfp.inc
+    frontend/A32/disassembler/disassembler.h
+    frontend/A32/disassembler/disassembler_arm.cpp
+    frontend/A32/disassembler/disassembler_thumb.cpp
     frontend/A32/FPSCR.h
     frontend/A32/ITState.h
     frontend/A32/PSR.h
@@ -119,6 +122,7 @@ add_library(dynarmic STATIC
     interface/A32/config.h
     interface/A32/coprocessor.h
     interface/A32/coprocessor_util.h
+    interface/A32/disassembler.h
     # A64
     frontend/A64/a64_ir_emitter.cpp
     frontend/A64/a64_ir_emitter.h

src/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler.h

@@ -0,0 +1,20 @@
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#pragma once
+
+#include <string>
+
+#include "dynarmic/common/common_types.h"
+
+namespace Dynarmic::A32 {
+
+std::string DisassembleArm(u32 instruction);
+std::string DisassembleThumb16(u16 instruction);
+
+}  // namespace Dynarmic::A32

src/dynarmic/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp

@@ -0,0 +1,397 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include <cstdlib>
+#include <string>
+
+#include <fmt/format.h>
+#include <fmt/ostream.h>
+#include <mcl/bit/bit_field.hpp>
+
+#include "dynarmic/common/string_util.h"
+#include "dynarmic/frontend/A32/a32_types.h"
+#include "dynarmic/frontend/A32/decoder/thumb16.h"
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
+#include "dynarmic/frontend/imm.h"
+
+namespace Dynarmic::A32 {
+
+class DisassemblerVisitor {
+public:
+    using instruction_return_type = std::string;
+
+    std::string thumb16_LSL_imm(Imm<5> imm5, Reg m, Reg d) {
+        return fmt::format("lsls {}, {}, #{}", d, m, imm5.ZeroExtend());
+    }
+
+    std::string thumb16_LSR_imm(Imm<5> imm5, Reg m, Reg d) {
+        const u32 shift = imm5 != 0 ? imm5.ZeroExtend() : 32U;
+        return fmt::format("lsrs {}, {}, #{}", d, m, shift);
+    }
+
+    std::string thumb16_ASR_imm(Imm<5> imm5, Reg m, Reg d) {
+        const u32 shift = imm5 != 0 ? imm5.ZeroExtend() : 32U;
+        return fmt::format("asrs {}, {}, #{}", d, m, shift);
+    }
+
+    std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
+        return fmt::format("adds {}, {}, {}", d, n, m);
+    }
+
+    std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) {
+        return fmt::format("subs {}, {}, {}", d, n, m);
+    }
+
+    std::string thumb16_ADD_imm_t1(Imm<3> imm3, Reg n, Reg d) {
+        return fmt::format("adds {}, {}, #{}", d, n, imm3.ZeroExtend());
+    }
+
+    std::string thumb16_SUB_imm_t1(Imm<3> imm3, Reg n, Reg d) {
+        return fmt::format("subs {}, {}, #{}", d, n, imm3.ZeroExtend());
+    }
+
+    std::string thumb16_MOV_imm(Reg d, Imm<8> imm8) {
+        return fmt::format("movs {}, #{}", d, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_CMP_imm(Reg n, Imm<8> imm8) {
+        return fmt::format("cmp {}, #{}", n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_ADD_imm_t2(Reg d_n, Imm<8> imm8) {
+        return fmt::format("adds {}, #{}", d_n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_SUB_imm_t2(Reg d_n, Imm<8> imm8) {
+        return fmt::format("subs {}, #{}", d_n, imm8.ZeroExtend());
+    }
+
+    std::string thumb16_AND_reg(Reg m, Reg d_n) {
+        return fmt::format("ands {}, {}", d_n, m);
+    }
+
+    std::string thumb16_EOR_reg(Reg m, Reg d_n) {
+        return fmt::format("eors {}, {}", d_n, m);
+    }
+
+    std::string thumb16_LSL_reg(Reg m, Reg d_n) {
+        return fmt::format("lsls {}, {}", d_n, m);
+    }
+
+    std::string thumb16_LSR_reg(Reg m, Reg d_n) {
+        return fmt::format("lsrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ASR_reg(Reg m, Reg d_n) {
+        return fmt::format("asrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ADC_reg(Reg m, Reg d_n) {
+        return fmt::format("adcs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_SBC_reg(Reg m, Reg d_n) {
+        return fmt::format("sbcs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_ROR_reg(Reg m, Reg d_n) {
+        return fmt::format("rors {}, {}", d_n, m);
+    }
+
+    std::string thumb16_TST_reg(Reg m, Reg n) {
+        return fmt::format("tst {}, {}", n, m);
+    }
+
+    std::string thumb16_RSB_imm(Reg n, Reg d) {
+        // Pre-UAL syntax: NEGS <Rd>, <Rn>
+        return fmt::format("rsbs {}, {}, #0", d, n);
+    }
+
+    std::string thumb16_CMP_reg_t1(Reg m, Reg n) {
+        return fmt::format("cmp {}, {}", n, m);
+    }
+
+    std::string thumb16_CMN_reg(Reg m, Reg n) {
+        return fmt::format("cmn {}, {}", n, m);
+    }
+
+    std::string thumb16_ORR_reg(Reg m, Reg d_n) {
+        return fmt::format("orrs {}, {}", d_n, m);
+    }
+
+    std::string thumb16_MUL_reg(Reg n, Reg d_m) {
+        return fmt::format("muls {}, {}, {}", d_m, n, d_m);
+    }
+
+    std::string thumb16_BIC_reg(Reg m, Reg d_n) {
+        return fmt::format("bics {}, {}", d_n, m);
+    }
+
+    std::string thumb16_MVN_reg(Reg m, Reg d) {
+        return fmt::format("mvns {}, {}", d, m);
+    }
+
+    std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
+        const Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
+        return fmt::format("add {}, {}", d_n, m);
+    }
+
+    std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
+        const Reg n = n_hi ? (n_lo + 8) : n_lo;
+        return fmt::format("cmp {}, {}", n, m);
+    }
+
+    std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
+        const Reg d = d_hi ? (d_lo + 8) : d_lo;
+        return fmt::format("mov {}, {}", d, m);
+    }
+
+    std::string thumb16_LDR_literal(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [pc, #{}]", t, imm32);
+    }
+
+    std::string thumb16_STR_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("str {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("strh {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("strb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrsb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldr {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrh {}, [%s, %s]", t, n, m);
+    }
+
+    std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrb {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) {
+        return fmt::format("ldrsh {}, [{}, {}]", t, n, m);
+    }
+
+    std::string thumb16_STR_imm_t1(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 2;
+        return fmt::format("str {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDR_imm_t1(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STRB_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend();
+        return fmt::format("strb {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDRB_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend();
+        return fmt::format("ldrb {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STRH_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 1;
+        return fmt::format("strh {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_LDRH_imm(Imm<5> imm5, Reg n, Reg t) {
+        const u32 imm32 = imm5.ZeroExtend() << 1;
+        return fmt::format("ldrh {}, [{}, #{}]", t, n, imm32);
+    }
+
+    std::string thumb16_STR_imm_t2(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("str {}, [sp, #{}]", t, imm32);
+    }
+
+    std::string thumb16_LDR_imm_t2(Reg t, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("ldr {}, [sp, #{}]", t, imm32);
+    }
+
+    std::string thumb16_ADR(Reg d, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("adr {}, +#{}", d, imm32);
+    }
+
+    std::string thumb16_ADD_sp_t1(Reg d, Imm<8> imm8) {
+        const u32 imm32 = imm8.ZeroExtend() << 2;
+        return fmt::format("add {}, sp, #{}", d, imm32);
+    }
+
+    std::string thumb16_ADD_sp_t2(Imm<7> imm7) {
+        const u32 imm32 = imm7.ZeroExtend() << 2;
+        return fmt::format("add sp, sp, #{}", imm32);
+    }
+
+    std::string thumb16_SUB_sp(Imm<7> imm7) {
+        const u32 imm32 = imm7.ZeroExtend() << 2;
+        return fmt::format("sub sp, sp, #{}", imm32);
+    }
+
+    std::string thumb16_NOP() {
+        return "nop";
+    }
+
+    std::string thumb16_SEV() {
+        return "sev";
+    }
+
+    std::string thumb16_SEVL() {
+        return "sevl";
+    }
+
+    std::string thumb16_WFE() {
+        return "wfe";
+    }
+
+    std::string thumb16_WFI() {
+        return "wfi";
+    }
+
+    std::string thumb16_YIELD() {
+        return "yield";
+    }
+
+    std::string thumb16_IT(Imm<8> imm8) {
+        const Cond firstcond = imm8.Bits<4, 7, Cond>();
+        const bool firstcond0 = imm8.Bit<4>();
+        const auto [x, y, z] = [&] {
+            if (imm8.Bits<0, 3>() == 0b1000) {
+                return std::make_tuple("", "", "");
+            }
+            if (imm8.Bits<0, 2>() == 0b100) {
+                return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", "", "");
+            }
+            if (imm8.Bits<0, 1>() == 0b10) {
+                return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", imm8.Bit<2>() == firstcond0 ? "t" : "e", "");
+            }
+            // Sanity note: Here imm8.Bit<0>() is guaranteed to be == 1. (imm8 can never be 0bxxxx0000)
+            return std::make_tuple(imm8.Bit<3>() == firstcond0 ? "t" : "e", imm8.Bit<2>() == firstcond0 ? "t" : "e", imm8.Bit<1>() == firstcond0 ? "t" : "e");
+        }();
+        return fmt::format("it{}{}{} {}", x, y, z, CondToString(firstcond));
+    }
+
+    std::string thumb16_SXTH(Reg m, Reg d) {
+        return fmt::format("sxth {}, {}", d, m);
+    }
+
+    std::string thumb16_SXTB(Reg m, Reg d) {
+        return fmt::format("sxtb {}, {}", d, m);
+    }
+
+    std::string thumb16_UXTH(Reg m, Reg d) {
+        return fmt::format("uxth {}, {}", d, m);
+    }
+
+    std::string thumb16_UXTB(Reg m, Reg d) {
+        return fmt::format("uxtb {}, {}", d, m);
+    }
+
+    std::string thumb16_PUSH(bool M, RegList reg_list) {
+        if (M)
+            reg_list |= 1 << 14;
+        return fmt::format("push {{{}}}", RegListToString(reg_list));
+    }
+
+    std::string thumb16_POP(bool P, RegList reg_list) {
+        if (P)
+            reg_list |= 1 << 15;
+        return fmt::format("pop {{{}}}", RegListToString(reg_list));
+    }
+
+    std::string thumb16_SETEND(bool E) {
+        return fmt::format("setend {}", E ? "BE" : "LE");
+    }
+
+    std::string thumb16_CPS(bool im, bool a, bool i, bool f) {
+        return fmt::format("cps{} {}{}{}", im ? "id" : "ie", a ? "a" : "", i ? "i" : "", f ? "f" : "");
+    }
+
+    std::string thumb16_REV(Reg m, Reg d) {
+        return fmt::format("rev {}, {}", d, m);
+    }
+
+    std::string thumb16_REV16(Reg m, Reg d) {
+        return fmt::format("rev16 {}, {}", d, m);
+    }
+
+    std::string thumb16_REVSH(Reg m, Reg d) {
+        return fmt::format("revsh {}, {}", d, m);
+    }
+
+    std::string thumb16_BKPT(Imm<8> imm8) {
+        return fmt::format("bkpt #{}", imm8.ZeroExtend());
+    }
+
+    std::string thumb16_STMIA(Reg n, RegList reg_list) {
+        return fmt::format("stm {}!, {{{}}}", n, RegListToString(reg_list));
+    }
+
+    std::string thumb16_LDMIA(Reg n, RegList reg_list) {
+        const bool write_back = !mcl::bit::get_bit(static_cast<size_t>(n), reg_list);
+        return fmt::format("ldm {}{}, {{{}}}", n, write_back ? "!" : "", RegListToString(reg_list));
+    }
+
+    std::string thumb16_BX(Reg m) {
+        return fmt::format("bx {}", m);
+    }
+
+    std::string thumb16_BLX_reg(Reg m) {
+        return fmt::format("blx {}", m);
+    }
+
+    std::string thumb16_CBZ_CBNZ(bool nonzero, Imm<1> i, Imm<5> imm5, Reg n) {
+        const char* const name = nonzero ? "cbnz" : "cbz";
+        const u32 imm = concatenate(i, imm5, Imm<1>{0}).ZeroExtend();
+
+        return fmt::format("{} {}, #{}", name, n, imm);
+    }
+
+    std::string thumb16_UDF() {
+        return fmt::format("udf");
+    }
+
+    std::string thumb16_SVC(Imm<8> imm8) {
+        return fmt::format("svc #{}", imm8.ZeroExtend());
+    }
+
+    std::string thumb16_B_t1(Cond cond, Imm<8> imm8) {
+        const s32 imm32 = static_cast<s32>((imm8.SignExtend<u32>() << 1) + 4);
+        return fmt::format("b{} {}#{}",
+                           CondToString(cond),
+                           Common::SignToChar(imm32),
+                           abs(imm32));
+    }
+
+    std::string thumb16_B_t2(Imm<11> imm11) {
+        const s32 imm32 = static_cast<s32>((imm11.SignExtend<u32>() << 1) + 4);
+        return fmt::format("b {}#{}",
+                           Common::SignToChar(imm32),
+                           abs(imm32));
+    }
+};
+
+std::string DisassembleThumb16(u16 instruction) {
+    DisassemblerVisitor visitor;
+    auto decoder = DecodeThumb16<DisassemblerVisitor>(instruction);
+    return !decoder ? fmt::format("UNKNOWN: {:x}", instruction) : decoder->get().call(visitor, instruction);
+}
+
+}  // namespace Dynarmic::A32

src/dynarmic/src/dynarmic/interface/A32/disassembler.h

@@ -0,0 +1,18 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#pragma once
+
+#include <cstdint>
+#include <string>
+
+namespace Dynarmic {
+namespace A32 {
+
+std::string DisassembleArm(std::uint32_t instruction);
+std::string DisassembleThumb16(std::uint16_t instruction);
+
+}  // namespace A32
+}  // namespace Dynarmic

src/dynarmic/tests/A32/fuzz_thumb.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -26,6 +26,7 @@
 #include "dynarmic/frontend/A32/FPSCR.h"
 #include "dynarmic/frontend/A32/PSR.h"
 #include "dynarmic/frontend/A32/a32_location_descriptor.h"
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
 #include "dynarmic/frontend/A32/translate/a32_translate.h"
 #include "dynarmic/interface/A32/a32.h"
 #include "dynarmic/ir/basic_block.h"

src/dynarmic/tests/A32/test_arm_disassembler.cpp

@@ -0,0 +1,381 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2016 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include <catch2/catch_test_macros.hpp>
+
+#include "dynarmic/frontend/A32/disassembler/disassembler.h"
+
+using Dynarmic::A32::DisassembleArm;
+
+TEST_CASE("Disassemble branch instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xEAFFFFFE) == "b +#0");
+    REQUIRE(DisassembleArm(0xEB000008) == "bl +#40");
+    REQUIRE(DisassembleArm(0xFBFFFFFE) == "blx +#2");
+    REQUIRE(DisassembleArm(0xFAFFFFFF) == "blx +#4");
+    REQUIRE(DisassembleArm(0xFBE1E7FE) == "blx -#7888894");
+    REQUIRE(DisassembleArm(0xE12FFF3D) == "blx sp");
+    REQUIRE(DisassembleArm(0x312FFF13) == "bxcc r3");
+    REQUIRE(DisassembleArm(0x012FFF29) == "bxjeq r9");
+}
+
+TEST_CASE("Disassemble data processing instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE2A21004) == "adc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0A21143) == "adc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0A21103) == "adc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0A21123) == "adc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0A21163) == "adc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0A21003) == "adc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0A21063) == "adc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0A21453) == "adc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0A21413) == "adc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0A21433) == "adc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0A21473) == "adc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2B21004) == "adcs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0B21143) == "adcs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0B21103) == "adcs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0B21123) == "adcs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0B21163) == "adcs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0B21003) == "adcs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0B21063) == "adcs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0B21453) == "adcs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0B21413) == "adcs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0B21433) == "adcs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0B21473) == "adcs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2853004) == "add r3, r5, #4");
+    REQUIRE(DisassembleArm(0xE0821143) == "add r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0821103) == "add r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0821123) == "add r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0821163) == "add r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0821003) == "add r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0821453) == "add r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0821413) == "add r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0821433) == "add r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0821473) == "add r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0821063) == "add r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2953004) == "adds r3, r5, #4");
+    REQUIRE(DisassembleArm(0xE0921143) == "adds r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0921103) == "adds r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0921123) == "adds r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0921163) == "adds r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0921003) == "adds r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0921063) == "adds r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0921453) == "adds r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0921413) == "adds r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0921433) == "adds r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0921473) == "adds r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2021004) == "and r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0021143) == "and r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0021103) == "and r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0021123) == "and r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0021163) == "and r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0021003) == "and r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0021453) == "and r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0021413) == "and r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0021433) == "and r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0021473) == "and r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0021063) == "and r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2121004) == "ands r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0121143) == "ands r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0121103) == "ands r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0121123) == "ands r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0121163) == "ands r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0121003) == "ands r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0121063) == "ands r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0121453) == "ands r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0121413) == "ands r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0121433) == "ands r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0121473) == "ands r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3C21004) == "bic r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1C21143) == "bic r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1C21103) == "bic r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1C21123) == "bic r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1C21163) == "bic r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1C21003) == "bic r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1C21453) == "bic r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1C21413) == "bic r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1C21433) == "bic r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1C21473) == "bic r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE1C21063) == "bic r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE3D21004) == "bics r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1D21143) == "bics r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1D21103) == "bics r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1D21123) == "bics r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1D21163) == "bics r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1D21003) == "bics r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1D21063) == "bics r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1D21453) == "bics r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1D21413) == "bics r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1D21433) == "bics r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1D21473) == "bics r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3710004) == "cmn r1, #4");
+    REQUIRE(DisassembleArm(0xE1710142) == "cmn r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1710102) == "cmn r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1710122) == "cmn r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1710162) == "cmn r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1710002) == "cmn r1, r2");
+    REQUIRE(DisassembleArm(0xE1710062) == "cmn r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1710352) == "cmn r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1710312) == "cmn r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1710332) == "cmn r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1710372) == "cmn r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3510004) == "cmp r1, #4");
+    REQUIRE(DisassembleArm(0xE1510142) == "cmp r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1510102) == "cmp r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1510122) == "cmp r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1510162) == "cmp r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1510002) == "cmp r1, r2");
+    REQUIRE(DisassembleArm(0xE1510062) == "cmp r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1510352) == "cmp r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1510312) == "cmp r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1510332) == "cmp r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1510372) == "cmp r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE2221004) == "eor r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0221243) == "eor r1, r2, r3, asr #4");
+    REQUIRE(DisassembleArm(0xE0221203) == "eor r1, r2, r3, lsl #4");
+    REQUIRE(DisassembleArm(0xE0221223) == "eor r1, r2, r3, lsr #4");
+    REQUIRE(DisassembleArm(0xE0221263) == "eor r1, r2, r3, ror #4");
+    REQUIRE(DisassembleArm(0xE0221003) == "eor r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0221453) == "eor r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0221413) == "eor r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0221433) == "eor r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0221473) == "eor r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0221063) == "eor r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE2321004) == "eors r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0321243) == "eors r1, r2, r3, asr #4");
+    REQUIRE(DisassembleArm(0xE0321203) == "eors r1, r2, r3, lsl #4");
+    REQUIRE(DisassembleArm(0xE0321223) == "eors r1, r2, r3, lsr #4");
+    REQUIRE(DisassembleArm(0xE0321263) == "eors r1, r2, r3, ror #4");
+    REQUIRE(DisassembleArm(0xE0321003) == "eors r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0321453) == "eors r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0321413) == "eors r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0321433) == "eors r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0321473) == "eors r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE0321063) == "eors r1, r2, r3, rrx");
+
+    REQUIRE(DisassembleArm(0xE3A010FF) == "mov r1, #255");
+    REQUIRE(DisassembleArm(0xE1A01142) == "mov r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1A01102) == "mov r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1A01122) == "mov r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1A01162) == "mov r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1A01062) == "mov r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1A0E00F) == "mov lr, pc");
+    REQUIRE(DisassembleArm(0xE3B010FF) == "movs r1, #255");
+    REQUIRE(DisassembleArm(0xE1B0E00F) == "movs lr, pc");
+    REQUIRE(DisassembleArm(0xE1B01142) == "movs r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1B01102) == "movs r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1B01122) == "movs r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1B01162) == "movs r1, r2, ror #2");
+
+    REQUIRE(DisassembleArm(0xE3E01004) == "mvn r1, #4");
+    REQUIRE(DisassembleArm(0xE1E01142) == "mvn r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1E01102) == "mvn r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1E01122) == "mvn r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1E01162) == "mvn r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1E01062) == "mvn r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1E01002) == "mvn r1, r2");
+    REQUIRE(DisassembleArm(0xE1E01352) == "mvn r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1E01312) == "mvn r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1E01332) == "mvn r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1E01372) == "mvn r1, r2, ror r3");
+    REQUIRE(DisassembleArm(0xE3F01004) == "mvns r1, #4");
+    REQUIRE(DisassembleArm(0xE1F01142) == "mvns r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1F01102) == "mvns r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1F01122) == "mvns r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1F01162) == "mvns r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1F01062) == "mvns r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1F01002) == "mvns r1, r2");
+    REQUIRE(DisassembleArm(0xE1F01352) == "mvns r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1F01312) == "mvns r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1F01332) == "mvns r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1F01372) == "mvns r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3821004) == "orr r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1821143) == "orr r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1821103) == "orr r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1821123) == "orr r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1821163) == "orr r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1821063) == "orr r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1821003) == "orr r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1821453) == "orr r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1821413) == "orr r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1821433) == "orr r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1821473) == "orr r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE3921004) == "orrs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE1921143) == "orrs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE1921103) == "orrs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE1921123) == "orrs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE1921163) == "orrs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE1921063) == "orrs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE1921003) == "orrs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE1921453) == "orrs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE1921413) == "orrs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE1921433) == "orrs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE1921473) == "orrs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2621004) == "rsb r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0621143) == "rsb r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0621103) == "rsb r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0621123) == "rsb r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0621163) == "rsb r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0621063) == "rsb r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0621003) == "rsb r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0621453) == "rsb r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0621413) == "rsb r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0621433) == "rsb r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0621473) == "rsb r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2721004) == "rsbs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0721143) == "rsbs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0721103) == "rsbs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0721123) == "rsbs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0721163) == "rsbs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0721063) == "rsbs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0721003) == "rsbs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0721453) == "rsbs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0721413) == "rsbs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0721433) == "rsbs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0721473) == "rsbs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2E21004) == "rsc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0E21143) == "rsc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0E21103) == "rsc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0E21123) == "rsc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0E21163) == "rsc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0E21063) == "rsc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0E21003) == "rsc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0E21453) == "rsc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0E21413) == "rsc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0E21433) == "rsc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0E21473) == "rsc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2F21004) == "rscs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0F21143) == "rscs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0F21103) == "rscs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0F21123) == "rscs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0F21163) == "rscs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0F21063) == "rscs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0F21003) == "rscs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0F21453) == "rscs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0F21413) == "rscs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0F21433) == "rscs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0F21473) == "rscs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE2C21004) == "sbc r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0C21143) == "sbc r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0C21103) == "sbc r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0C21123) == "sbc r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0C21163) == "sbc r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0C21063) == "sbc r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0C21003) == "sbc r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0C21453) == "sbc r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0C21413) == "sbc r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0C21433) == "sbc r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0C21473) == "sbc r1, r2, r3, ror r4");
+    REQUIRE(DisassembleArm(0xE2D21004) == "sbcs r1, r2, #4");
+    REQUIRE(DisassembleArm(0xE0D21143) == "sbcs r1, r2, r3, asr #2");
+    REQUIRE(DisassembleArm(0xE0D21103) == "sbcs r1, r2, r3, lsl #2");
+    REQUIRE(DisassembleArm(0xE0D21123) == "sbcs r1, r2, r3, lsr #2");
+    REQUIRE(DisassembleArm(0xE0D21163) == "sbcs r1, r2, r3, ror #2");
+    REQUIRE(DisassembleArm(0xE0D21063) == "sbcs r1, r2, r3, rrx");
+    REQUIRE(DisassembleArm(0xE0D21003) == "sbcs r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0D21453) == "sbcs r1, r2, r3, asr r4");
+    REQUIRE(DisassembleArm(0xE0D21413) == "sbcs r1, r2, r3, lsl r4");
+    REQUIRE(DisassembleArm(0xE0D21433) == "sbcs r1, r2, r3, lsr r4");
+    REQUIRE(DisassembleArm(0xE0D21473) == "sbcs r1, r2, r3, ror r4");
+
+    REQUIRE(DisassembleArm(0xE3310004) == "teq r1, #4");
+    REQUIRE(DisassembleArm(0xE1310142) == "teq r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1310102) == "teq r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1310122) == "teq r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1310162) == "teq r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1310002) == "teq r1, r2");
+    REQUIRE(DisassembleArm(0xE1310062) == "teq r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1310352) == "teq r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1310312) == "teq r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1310332) == "teq r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1310372) == "teq r1, r2, ror r3");
+
+    REQUIRE(DisassembleArm(0xE3110004) == "tst r1, #4");
+    REQUIRE(DisassembleArm(0xE1110142) == "tst r1, r2, asr #2");
+    REQUIRE(DisassembleArm(0xE1110102) == "tst r1, r2, lsl #2");
+    REQUIRE(DisassembleArm(0xE1110122) == "tst r1, r2, lsr #2");
+    REQUIRE(DisassembleArm(0xE1110162) == "tst r1, r2, ror #2");
+    REQUIRE(DisassembleArm(0xE1110002) == "tst r1, r2");
+    REQUIRE(DisassembleArm(0xE1110062) == "tst r1, r2, rrx");
+    REQUIRE(DisassembleArm(0xE1110352) == "tst r1, r2, asr r3");
+    REQUIRE(DisassembleArm(0xE1110312) == "tst r1, r2, lsl r3");
+    REQUIRE(DisassembleArm(0xE1110332) == "tst r1, r2, lsr r3");
+    REQUIRE(DisassembleArm(0xE1110372) == "tst r1, r2, ror r3");
+}
+
+TEST_CASE("Disassemble half-word multiply and multiply accumulate instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE1003281) == "smlabb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032C1) == "smlabt r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032A1) == "smlatb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE10032E1) == "smlatt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE1203281) == "smlawb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE12032C1) == "smlawt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE12002A1) == "smulwb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE12002E1) == "smulwt r0, r1, r2");
+
+    REQUIRE(DisassembleArm(0xE1410382) == "smlalbb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103C2) == "smlalbt r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103A2) == "smlaltb r0, r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE14103E2) == "smlaltt r0, r1, r2, r3");
+
+    REQUIRE(DisassembleArm(0xE1600281) == "smulbb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002C1) == "smulbt r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002A1) == "smultb r0, r1, r2");
+    REQUIRE(DisassembleArm(0xE16002E1) == "smultt r0, r1, r2");
+}
+
+TEST_CASE("Disassemble multiply and multiply accumulate instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE0214392) == "mla r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0314392) == "mlas r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0010392) == "mul r1, r2, r3");
+    REQUIRE(DisassembleArm(0xE0110392) == "muls r1, r2, r3");
+
+    // TODO: MLS should be here whenever it's supported.
+
+    REQUIRE(DisassembleArm(0xE0E21493) == "smlal r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0F21493) == "smlals r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0C21493) == "smull r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0D21493) == "smulls r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0421493) == "umaal r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0A21493) == "umlal r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0B21493) == "umlals r1, r2, r3, r4");
+
+    REQUIRE(DisassembleArm(0xE0821493) == "umull r1, r2, r3, r4");
+    REQUIRE(DisassembleArm(0xE0921493) == "umulls r1, r2, r3, r4");
+}
+
+TEST_CASE("Disassemble synchronization primitive instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE1921F9F) == "ldrex r1, [r2]");
+    REQUIRE(DisassembleArm(0xE1D21F9F) == "ldrexb r1, [r2]");
+    REQUIRE(DisassembleArm(0xE1B31F9F) == "ldrexd r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1F21F9F) == "ldrexh r1, [r2]");
+
+    REQUIRE(DisassembleArm(0xE1831F92) == "strex r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1C31F92) == "strexb r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1A41F92) == "strexd r1, r2, r3, [r4]");
+    REQUIRE(DisassembleArm(0xE1E31F92) == "strexh r1, r2, [r3]");
+
+    REQUIRE(DisassembleArm(0xE1031092) == "swp r1, r2, [r3]");
+    REQUIRE(DisassembleArm(0xE1431092) == "swpb r1, r2, [r3]");
+}
+
+TEST_CASE("Disassemble load / store multiple instructions", "[arm][disassembler]") {
+    REQUIRE(DisassembleArm(0xE92D500F) == "stmdb sp!, {r0, r1, r2, r3, r12, lr}");
+}

src/dynarmic/tests/CMakeLists.txt

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+# SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 # SPDX-License-Identifier: GPL-3.0-or-later
 include(TargetArchitectureSpecificSources)
 
@@ -9,6 +9,7 @@ add_executable(dynarmic_tests
     fp/unpacked_tests.cpp
     rand_int.h
     # A32
+    A32/test_arm_disassembler.cpp
     A32/test_arm_instructions.cpp
     A32/test_coprocessor.cpp
     A32/test_svc.cpp

src/dynarmic/tests/print_info.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 /* This file is part of the dynarmic project.
@@ -34,6 +34,7 @@
 #include "dynarmic/frontend/A64/translate/impl/impl.h"
 #include "dynarmic/interface/A32/a32.h"
 #include "dynarmic/interface/A32/config.h"
+#include "dynarmic/interface/A32/disassembler.h"
 #include "dynarmic/ir/basic_block.h"
 #include "dynarmic/ir/opt_passes.h"
 

src/frontend_common/settings_generator.cpp

@@ -11,9 +11,8 @@ namespace FrontendCommon {
 void GenerateSettings() {
     static std::random_device rd;
 
-    // Web Token //
-    auto &token_setting = Settings::values.eden_token;
-    if (token_setting.GetValue().empty()) {
+    // Web Token
+    if (Settings::values.eden_token.GetValue().empty()) {
         static constexpr const size_t token_length = 48;
         static constexpr const frozen::string token_set = "abcdefghijklmnopqrstuvwxyz";
         static std::uniform_int_distribution<int> token_dist(0, token_set.size() - 1);
@@ -23,9 +22,18 @@ void GenerateSettings() {
             size_t idx = token_dist(rd);
             result += token_set[idx];
         }
-
-        token_setting.SetValue(result);
+        Settings::values.eden_token.SetValue(result);
     }
+
+    // Randomly generated number because, well, we fill the rest automagically ;)
+    // Other serial parts are filled by Region_Index
+    std::random_device device;
+    std::mt19937 gen(device());
+    std::uniform_int_distribution<u32> distribution(1, (std::numeric_limits<u32>::max)());
+    if (Settings::values.serial_unit.GetValue() == 0)
+        Settings::values.serial_unit.SetValue(distribution(gen));
+    if (Settings::values.serial_battery.GetValue() == 0)
+        Settings::values.serial_battery.SetValue(distribution(gen));
 }
 
 }

src/qt_common/config/shared_translation.cpp

@@ -517,8 +517,8 @@ std::unique_ptr<ComboboxTranslationMap> ComboboxEnumeration(QObject* parent)
                               PAIR(FramePacingMode, Target_Auto, tr("Auto")),
                               PAIR(FramePacingMode, Target_30, tr("30 FPS")),
                               PAIR(FramePacingMode, Target_60, tr("60 FPS")),
+                              PAIR(FramePacingMode, Target_90, tr("90 FPS")),
                               PAIR(FramePacingMode, Target_120, tr("120 FPS")),
-                              PAIR(FramePacingMode, Target_240, tr("240 FPS")),
                           }});
     translations->insert({Settings::EnumMetadata<Settings::VramUsageMode>::Index(),
                           {

src/video_core/renderer_vulkan/vk_scheduler.cpp

@@ -347,7 +347,7 @@ void Scheduler::EndRenderPass()
         Record([num_images = num_renderpass_images,
                        images = renderpass_images,
                        ranges = renderpass_image_ranges](vk::CommandBuffer cmdbuf) {
-            std::vector<VkImageMemoryBarrier> barriers(num_images);
+            std::array<VkImageMemoryBarrier, 9> barriers;
             VkPipelineStageFlags src_stages = 0;
             for (size_t i = 0; i < num_images; ++i) {
                 const VkImageSubresourceRange& range = ranges[i];

src/video_core/renderer_vulkan/vk_scheduler.h

@@ -115,28 +115,27 @@ public:
     /// Waits for the given GPU tick, optionally pacing frames.
     void Wait(u64 tick, double target_fps = 0.0) {
         if (Settings::values.use_speed_limit.GetValue() && target_fps > 0.0) {
-            auto frame_duration = std::chrono::duration_cast<std::chrono::steady_clock::duration>(std::chrono::duration<double>(1.0 / target_fps));
-            auto now = std::chrono::steady_clock::now();
-            if (now < next_frame_time) {
-                std::this_thread::sleep_until(next_frame_time);
-                next_frame_time += frame_duration;
+            const auto now = std::chrono::steady_clock::now();
+            if (start_time == std::chrono::steady_clock::time_point{} || current_target_fps != target_fps) {
+                start_time = now;
+                frame_counter = 0;
+                current_target_fps = target_fps;
+            }
+            frame_counter++;
+            std::chrono::duration<double> frame_interval(1.0 / current_target_fps);
+            auto target_time = start_time + frame_interval * frame_counter;
+            if (target_time > now) {
+                std::this_thread::sleep_until(target_time);
             } else {
-                next_frame_time = now + frame_duration;
+                start_time = now;
+                frame_counter = 0;
             }
         }
-        if (tick > master_semaphore->CurrentTick() && !chunk->Empty()) {
-            Flush();
-        }
-        master_semaphore->Wait(tick);
-    }
-
-    /// Resets the frame pacing state by setting the next frame time.
-    void ResetFramePacing(double target_fps = 0.0) {
-        if (target_fps > 0.0) {
-            auto frame_duration = std::chrono::duration_cast<std::chrono::steady_clock::duration>(std::chrono::duration<double>(1.0 / target_fps));
-            next_frame_time = std::chrono::steady_clock::now() + frame_duration;
-        } else {
-            next_frame_time = std::chrono::steady_clock::time_point{};
+        if (tick > 0) {
+            if (tick >= master_semaphore->CurrentTick()) {
+                Flush();
+            }
+            master_semaphore->Wait(tick);
         }
     }
 
@@ -282,7 +281,9 @@ private:
     std::condition_variable_any event_cv;
     std::jthread worker_thread;
 
-    std::chrono::steady_clock::time_point next_frame_time{};
+    std::chrono::steady_clock::time_point start_time{};
+    u64 frame_counter{};
+    double current_target_fps{};
 };
 
 } // namespace Vulkan

src/video_core/renderer_vulkan/vk_swapchain.cpp

@@ -146,25 +146,6 @@ void Swapchain::Create(
 {
     is_outdated = false;
     is_suboptimal = false;
-
-    switch (Settings::values.frame_pacing_mode.GetValue()) {
-    case Settings::FramePacingMode::Target_Auto:
-        scheduler.ResetFramePacing();
-        break;
-    case Settings::FramePacingMode::Target_30:
-        scheduler.ResetFramePacing(30.0);
-        break;
-    case Settings::FramePacingMode::Target_60:
-        scheduler.ResetFramePacing(60.0);
-        break;
-    case Settings::FramePacingMode::Target_120:
-        scheduler.ResetFramePacing(120.0);
-        break;
-    case Settings::FramePacingMode::Target_240:
-        scheduler.ResetFramePacing(240.0);
-        break;
-    }
-
     width = width_;
     height = height_;
 #ifdef ANDROID
@@ -213,24 +194,22 @@ bool Swapchain::AcquireNextImage() {
         break;
     }
 
-    if (resource_ticks[image_index] != 0 && !scheduler.IsFree(resource_ticks[image_index])) {
-        switch (Settings::values.frame_pacing_mode.GetValue()) {
-        case Settings::FramePacingMode::Target_Auto:
-            scheduler.Wait(resource_ticks[image_index]);
-            break;
-        case Settings::FramePacingMode::Target_30:
-            scheduler.Wait(resource_ticks[image_index], 30.0);
-            break;
-        case Settings::FramePacingMode::Target_60:
-            scheduler.Wait(resource_ticks[image_index], 60.0);
-            break;
-        case Settings::FramePacingMode::Target_120:
-            scheduler.Wait(resource_ticks[image_index], 120.0);
-            break;
-        case Settings::FramePacingMode::Target_240:
-            scheduler.Wait(resource_ticks[image_index], 240.0);
-            break;
-        }
+    switch (Settings::values.frame_pacing_mode.GetValue()) {
+    case Settings::FramePacingMode::Target_Auto:
+        scheduler.Wait(resource_ticks[image_index]);
+        break;
+    case Settings::FramePacingMode::Target_30:
+        scheduler.Wait(resource_ticks[image_index], 30.0);
+        break;
+    case Settings::FramePacingMode::Target_60:
+        scheduler.Wait(resource_ticks[image_index], 60.0);
+        break;
+    case Settings::FramePacingMode::Target_90:
+        scheduler.Wait(resource_ticks[image_index], 90.0);
+        break;
+    case Settings::FramePacingMode::Target_120:
+        scheduler.Wait(resource_ticks[image_index], 120.0);
+        break;
     }
 
     resource_ticks[image_index] = scheduler.CurrentTick();

src/yuzu/configuration/configure_debug.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: 2016 Citra Emulator Project
@@ -57,10 +57,6 @@ void ConfigureDebug::SetConfiguration() {
 #endif
 
     // Immutable after starting
-    ui->serial_battery_edit->setEnabled(runtime_lock);
-    ui->serial_battery_edit->setText(QString::fromStdString(Settings::values.serial_battery.GetValue()));
-    ui->serial_board_edit->setEnabled(runtime_lock);
-    ui->serial_board_edit->setText(QString::fromStdString(Settings::values.serial_unit.GetValue()));
     ui->homebrew_args_edit->setEnabled(runtime_lock);
     ui->homebrew_args_edit->setText(QString::fromStdString(Settings::values.program_args.GetValue()));
     ui->toggle_console->setEnabled(runtime_lock);