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xbzk
b85f289048
Contains the minimal set of functionalities to allow tico installer succeed, and tico work normally EXCEPT for game launching (which me or someone else will investigate later) First three commits are from PR 4012. The other six, kinda dizzy to explain each one. All were implemented based on tico source, switchbrew and libnx. Hopefully the commit messages will do. Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/4086 Reviewed-by: Lizzie <lizzie@eden-emu.dev> Reviewed-by: Maufeat <sahyno1996@gmail.com>
74 lines
2.7 KiB
C++
74 lines
2.7 KiB
C++
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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// SPDX-FileCopyrightText: 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#include "common/assert.h"
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#include "video_core/control/channel_state.h"
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#include "video_core/dma_pusher.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/engines/puller.h"
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#include "video_core/memory_manager.h"
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namespace Tegra::Control {
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namespace {
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// Match NVK/Nouveau's initial pushbuffer subchannel layout.
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constexpr u32 Nvk3DSubchannel = 0;
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constexpr u32 NvkComputeSubchannel = 1;
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constexpr u32 Nvk2DSubchannel = 3;
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constexpr u32 NvkCopySubchannel = 4;
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void BindNvkDefaultSubchannels(ChannelState::Payload& payload) {
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auto& dma_pusher = payload.dma_pusher;
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dma_pusher.BindSubchannel(&payload.maxwell_3d, Nvk3DSubchannel, Engines::EngineTypes::Maxwell3D);
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dma_pusher.BindSubchannel(&payload.kepler_compute, NvkComputeSubchannel,
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Engines::EngineTypes::KeplerCompute);
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// Subchannel 2 is M2MF there; Eden does not expose a 0x9039 engine yet.
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dma_pusher.BindSubchannel(&payload.fermi_2d, Nvk2DSubchannel, Engines::EngineTypes::Fermi2D);
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dma_pusher.BindSubchannel(&payload.maxwell_dma, NvkCopySubchannel,
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Engines::EngineTypes::MaxwellDMA);
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}
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} // Anonymous namespace
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ChannelState::Payload::Payload(Core::System& system, MemoryManager& memory_manager, ChannelState& channel_state)
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: maxwell_3d(memory_manager)
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, fermi_2d(memory_manager)
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, kepler_compute(memory_manager)
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, maxwell_dma(memory_manager)
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, kepler_memory(memory_manager)
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, nv01_timer(memory_manager)
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, dma_pusher(system, memory_manager, channel_state)
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{}
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ChannelState::ChannelState(s32 bind_id_)
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: bind_id{bind_id_}
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{}
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void ChannelState::Init(Core::System& system, u64 program_id_) {
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ASSERT(memory_manager);
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program_id = program_id_;
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payload.emplace(system, *memory_manager, *this);
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BindNvkDefaultSubchannels(*payload);
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initialized = true;
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}
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void ChannelState::BindRasterizer(VideoCore::RasterizerInterface* rasterizer) {
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payload->dma_pusher.BindRasterizer(rasterizer);
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memory_manager->BindRasterizer(rasterizer);
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payload->maxwell_3d.BindRasterizer(rasterizer);
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payload->fermi_2d.BindRasterizer(rasterizer);
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payload->kepler_memory.BindRasterizer(rasterizer);
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payload->kepler_compute.BindRasterizer(rasterizer);
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payload->maxwell_dma.BindRasterizer(rasterizer);
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//payload->nv01_timer.BindRasterizer(rasterizer);
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}
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} // namespace Tegra::Control
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