mirror of
https://git.eden-emu.dev/eden-emu/eden.git
synced 2026-08-18 06:10:35 +00:00
CamilleLaVey
372bdfccbc
This is the first step into the conversion on full GPU video decoding for Android; currently due to the VIC structure, I couldn't set it on surface mode to prevent the latency when sending video decoded (which is processed by GPU now), because currently we convert YUV420 into the Nvidia's format each frame constantly on CPU, aside the requirements from other extensions to work + VIC rewrite, which is a work currently not planned to happen on this PR; the actual configuration for video decoding is ByteBuffer, using GPU to decode NVDEC data (all codecs supported, h264, vp8 and vp9) and send it to CPU for display purposes, which is more faster than relying purely on CPU for any drawing task, saving devices resources/ heating, the downside on this will be the slight latency when a new frame is displayed, which is gonna be a black frame for less than a second, nothing major to harm the experience rather than actually trying our best to take advantage on hardware accelerated. Aside this, I also added a bunch of minor Vulkan fixes to grant drivers less thinkering when receiving spir-v instructions, meaning this has new bans for extensions on QCOM (following reported issues on other projects working around Adreno driver behavior), this more than providing performance aims to enhance the stability on the driver, performance it's gonna likely to be hit based on the UBO's (StorageBufferAccess) operations and SSBO (uniformStorageBufferAccess), there was an already existing path for the emulation which forces to wide them into 32bit packed operations. I also included some smaller changes/ bugs + VUID's fixes from earlier changes on my work. Special Thanks: -> Mr. Smoly Gidolard (@gidoly) Sources: 1.- https://github.com/microsoft/DirectXShaderCompiler/issues/2842 2.- https://github.com/mlc-ai/web-llm/issues/836 3.- https://github.com/ggml-org/llama.cpp/issues/5186 4.- https://github.com/encounter/aurora/pull/202 Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/4191
581 lines
23 KiB
C++
581 lines
23 KiB
C++
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <span>
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#include <tuple>
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#include <type_traits>
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#include <utility>
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#include <vector>
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#include "common/settings.h"
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/program.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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template <class Func>
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struct FuncTraits {};
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template <class ReturnType_, class... Args>
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struct FuncTraits<ReturnType_ (*)(Args...)> {
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using ReturnType = ReturnType_;
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static constexpr size_t NUM_ARGS = sizeof...(Args);
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template <size_t I>
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using ArgType = std::tuple_element_t<I, std::tuple<Args...>>;
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};
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#ifdef _MSC_VER
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#pragma warning(push)
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#pragma warning(disable : 4702) // Ignore unreachable code warning
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#endif
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template <auto func, typename... Args>
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void SetDefinition(EmitContext& ctx, IR::Inst* inst, Args... args) {
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inst->SetDefinition<Id>(func(ctx, std::forward<Args>(args)...));
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}
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#ifdef _MSC_VER
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#pragma warning(pop)
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#endif
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template <typename ArgType>
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ArgType Arg(EmitContext& ctx, const IR::Value& arg) {
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if constexpr (std::is_same_v<ArgType, Id>) {
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return ctx.Def(arg);
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} else if constexpr (std::is_same_v<ArgType, const IR::Value&>) {
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return arg;
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} else if constexpr (std::is_same_v<ArgType, u32>) {
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return arg.U32();
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} else if constexpr (std::is_same_v<ArgType, IR::Attribute>) {
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return arg.Attribute();
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} else if constexpr (std::is_same_v<ArgType, IR::Patch>) {
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return arg.Patch();
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} else if constexpr (std::is_same_v<ArgType, IR::Reg>) {
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return arg.Reg();
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}
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}
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template <auto func, bool is_first_arg_inst, size_t... I>
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void Invoke(EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) {
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using Traits = FuncTraits<decltype(func)>;
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if constexpr (std::is_same_v<typename Traits::ReturnType, Id>) {
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if constexpr (is_first_arg_inst) {
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SetDefinition<func>(
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ctx, inst, inst,
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Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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SetDefinition<func>(
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ctx, inst, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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} else {
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if constexpr (is_first_arg_inst) {
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func(ctx, inst, Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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func(ctx, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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}
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}
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template <auto func>
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void Invoke(EmitContext& ctx, IR::Inst* inst) {
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using Traits = FuncTraits<decltype(func)>;
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static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments");
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if constexpr (Traits::NUM_ARGS == 1) {
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Invoke<func, false>(ctx, inst, std::make_index_sequence<0>{});
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} else {
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using FirstArgType = typename Traits::template ArgType<1>;
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static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>;
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using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>;
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Invoke<func, is_first_arg_inst>(ctx, inst, Indices{});
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}
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}
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void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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switch (inst->GetOpcode()) {
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#define OPCODE(name, result_type, ...) \
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case IR::Opcode::name: \
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return Invoke<&Emit##name>(ctx, inst);
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#include "shader_recompiler/frontend/ir/opcodes.inc"
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#undef OPCODE
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}
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throw LogicError("Invalid opcode {}", inst->GetOpcode());
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}
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Id TypeId(const EmitContext& ctx, IR::Type type) {
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switch (type) {
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case IR::Type::U1:
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return ctx.U1;
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case IR::Type::U32:
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return ctx.U32[1];
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default:
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throw NotImplementedException("Phi node type {}", type);
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}
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}
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void Traverse(EmitContext& ctx, IR::Program& program) {
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IR::Block* current_block{};
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for (const IR::AbstractSyntaxNode& node : program.syntax_list) {
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switch (node.type) {
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case IR::AbstractSyntaxNode::Type::Block: {
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const Id label{node.data.block->Definition<Id>()};
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if (current_block) {
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ctx.OpBranch(label);
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}
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current_block = node.data.block;
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ctx.AddLabel(label);
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for (IR::Inst& inst : node.data.block->Instructions()) {
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EmitInst(ctx, &inst);
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}
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break;
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}
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case IR::AbstractSyntaxNode::Type::If: {
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const Id if_label{node.data.if_node.body->Definition<Id>()};
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const Id endif_label{node.data.if_node.merge->Definition<Id>()};
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ctx.OpSelectionMerge(endif_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(ctx.Def(node.data.if_node.cond), if_label, endif_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Loop: {
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const Id body_label{node.data.loop.body->Definition<Id>()};
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const Id continue_label{node.data.loop.continue_block->Definition<Id>()};
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const Id endloop_label{node.data.loop.merge->Definition<Id>()};
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ctx.OpLoopMerge(endloop_label, continue_label, spv::LoopControlMask::MaskNone);
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ctx.OpBranch(body_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Break: {
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const Id break_label{node.data.break_node.merge->Definition<Id>()};
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const Id skip_label{node.data.break_node.skip->Definition<Id>()};
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ctx.OpBranchConditional(ctx.Def(node.data.break_node.cond), break_label, skip_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::EndIf:
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if (current_block) {
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ctx.OpBranch(node.data.end_if.merge->Definition<Id>());
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}
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break;
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case IR::AbstractSyntaxNode::Type::Repeat: {
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Id cond{ctx.Def(node.data.repeat.cond)};
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if (!Settings::values.disable_shader_loop_safety_checks) {
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const Id pointer_type{ctx.TypePointer(spv::StorageClass::Private, ctx.U32[1])};
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const Id safety_counter{ctx.AddGlobalVariable(
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pointer_type, spv::StorageClass::Private, ctx.Const(0x2000u))};
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if (ctx.profile.supported_spirv >= 0x00010400) {
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ctx.interfaces.push_back(safety_counter);
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}
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const Id old_counter{ctx.OpLoad(ctx.U32[1], safety_counter)};
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const Id new_counter{ctx.OpISub(ctx.U32[1], old_counter, ctx.Const(1u))};
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ctx.OpStore(safety_counter, new_counter);
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const Id safety_cond{
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ctx.OpSGreaterThanEqual(ctx.U1, new_counter, ctx.u32_zero_value)};
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cond = ctx.OpLogicalAnd(ctx.U1, cond, safety_cond);
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}
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const Id loop_header_label{node.data.repeat.loop_header->Definition<Id>()};
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const Id merge_label{node.data.repeat.merge->Definition<Id>()};
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ctx.OpBranchConditional(cond, loop_header_label, merge_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Return:
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ctx.OpReturn();
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break;
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case IR::AbstractSyntaxNode::Type::Unreachable:
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ctx.OpUnreachable();
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break;
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}
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if (node.type != IR::AbstractSyntaxNode::Type::Block) {
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current_block = nullptr;
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}
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}
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}
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Id DefineMain(EmitContext& ctx, IR::Program& program) {
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const Id void_function{ctx.TypeFunction(ctx.void_id)};
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const Id main{ctx.OpFunction(ctx.void_id, spv::FunctionControlMask::MaskNone, void_function)};
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for (IR::Block* const block : program.blocks) {
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block->SetDefinition(ctx.OpLabel());
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}
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Traverse(ctx, program);
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ctx.OpFunctionEnd();
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return main;
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}
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spv::ExecutionMode ExecutionMode(TessPrimitive primitive) {
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switch (primitive) {
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case TessPrimitive::Isolines:
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return spv::ExecutionMode::Isolines;
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case TessPrimitive::Triangles:
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return spv::ExecutionMode::Triangles;
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case TessPrimitive::Quads:
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return spv::ExecutionMode::Quads;
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}
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throw InvalidArgument("Tessellation primitive {}", primitive);
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}
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spv::ExecutionMode ExecutionMode(TessSpacing spacing) {
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switch (spacing) {
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case TessSpacing::Equal:
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return spv::ExecutionMode::SpacingEqual;
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case TessSpacing::FractionalOdd:
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return spv::ExecutionMode::SpacingFractionalOdd;
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case TessSpacing::FractionalEven:
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return spv::ExecutionMode::SpacingFractionalEven;
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}
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throw InvalidArgument("Tessellation spacing {}", spacing);
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}
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void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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const std::span interfaces(ctx.interfaces.data(), ctx.interfaces.size());
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spv::ExecutionModel execution_model{};
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switch (program.stage) {
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case Stage::Compute: {
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const std::array<u32, 3> workgroup_size{program.workgroup_size};
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execution_model = spv::ExecutionModel::GLCompute;
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ctx.AddExecutionMode(main, spv::ExecutionMode::LocalSize, workgroup_size[0],
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workgroup_size[1], workgroup_size[2]);
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break;
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}
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case Stage::VertexB:
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execution_model = spv::ExecutionModel::Vertex;
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break;
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case Stage::TessellationControl:
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execution_model = spv::ExecutionModel::TessellationControl;
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ctx.AddCapability(spv::Capability::Tessellation);
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices, program.invocations);
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break;
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case Stage::TessellationEval:
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execution_model = spv::ExecutionModel::TessellationEvaluation;
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ctx.AddCapability(spv::Capability::Tessellation);
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ctx.AddExecutionMode(main, ExecutionMode(ctx.runtime_info.tess_primitive));
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ctx.AddExecutionMode(main, ExecutionMode(ctx.runtime_info.tess_spacing));
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ctx.AddExecutionMode(main, ctx.runtime_info.tess_clockwise
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? spv::ExecutionMode::VertexOrderCw
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: spv::ExecutionMode::VertexOrderCcw);
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break;
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case Stage::Geometry:
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execution_model = spv::ExecutionModel::Geometry;
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ctx.AddCapability(spv::Capability::Geometry);
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if (ctx.profile.support_geometry_streams) {
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ctx.AddCapability(spv::Capability::GeometryStreams);
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}
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switch (ctx.runtime_info.input_topology) {
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case InputTopology::Points:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputPoints);
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break;
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case InputTopology::Lines:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputLines);
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break;
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case InputTopology::LinesAdjacency:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputLinesAdjacency);
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break;
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case InputTopology::Triangles:
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ctx.AddExecutionMode(main, spv::ExecutionMode::Triangles);
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break;
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case InputTopology::TrianglesAdjacency:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputTrianglesAdjacency);
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break;
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}
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switch (program.output_topology) {
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case OutputTopology::PointList:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputPoints);
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break;
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case OutputTopology::LineStrip:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputLineStrip);
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break;
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case OutputTopology::TriangleStrip:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputTriangleStrip);
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break;
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}
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if (program.info.stores[IR::Attribute::PointSize]) {
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ctx.AddCapability(spv::Capability::GeometryPointSize);
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}
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices, program.output_vertices);
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ctx.AddExecutionMode(main, spv::ExecutionMode::Invocations, program.invocations);
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if (program.is_geometry_passthrough) {
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if (ctx.profile.support_geometry_shader_passthrough) {
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ctx.AddExtension("SPV_NV_geometry_shader_passthrough");
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ctx.AddCapability(spv::Capability::GeometryShaderPassthroughNV);
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} else {
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LOG_WARNING(Shader_SPIRV, "Geometry shader passthrough used with no support");
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}
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}
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break;
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case Stage::Fragment:
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execution_model = spv::ExecutionModel::Fragment;
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if (ctx.profile.lower_left_origin_mode) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginLowerLeft);
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} else {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginUpperLeft);
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}
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if (program.info.stores_frag_depth) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::DepthReplacing);
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}
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if (ctx.runtime_info.force_early_z) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::EarlyFragmentTests);
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}
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break;
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default:
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throw NotImplementedException("Stage {}", program.stage);
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}
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ctx.AddEntryPoint(execution_model, main, "main", interfaces);
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}
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void SetupDenormControl(const Profile& profile, const IR::Program& program, EmitContext& ctx,
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Id main_func) {
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const Info& info{program.info};
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if (info.uses_fp32_denorms_flush && info.uses_fp32_denorms_preserve) {
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LOG_DEBUG(Shader_SPIRV, "Fp32 denorm flush and preserve on the same shader");
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} else if (info.uses_fp32_denorms_flush) {
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if (profile.support_fp32_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 32U);
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} else {
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// Drivers will most likely flush denorms by default, no need to warn
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}
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} else if (info.uses_fp32_denorms_preserve) {
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if (profile.support_fp32_denorm_preserve) {
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ctx.AddCapability(spv::Capability::DenormPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormPreserve, 32U);
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} else {
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LOG_DEBUG(Shader_SPIRV, "Fp32 denorm preserve used in shader without host support");
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}
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}
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if (!profile.support_separate_denorm_behavior || profile.has_broken_fp16_float_controls) {
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// No separate denorm behavior
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return;
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}
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if (info.uses_fp16_denorms_flush && info.uses_fp16_denorms_preserve) {
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LOG_DEBUG(Shader_SPIRV, "Fp16 denorm flush and preserve on the same shader");
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} else if (info.uses_fp16_denorms_flush) {
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if (profile.support_fp16_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 16U);
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} else {
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// Same as fp32, no need to warn as most drivers will flush by default
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}
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} else if (info.uses_fp16_denorms_preserve) {
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if (profile.support_fp16_denorm_preserve) {
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ctx.AddCapability(spv::Capability::DenormPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormPreserve, 16U);
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} else {
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LOG_DEBUG(Shader_SPIRV, "Fp16 denorm preserve used in shader without host support");
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}
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}
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}
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void SetupSignedNanCapabilities(const Profile& profile, const IR::Program& program,
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EmitContext& ctx, Id main_func) {
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if (profile.has_broken_fp16_float_controls && program.info.uses_fp16) {
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return;
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}
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if (program.info.uses_fp16 && profile.support_fp16_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 16U);
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}
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if (profile.support_fp32_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 32U);
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}
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if (program.info.uses_fp64 && profile.support_fp64_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 64U);
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}
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}
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void SetupTransformFeedbackCapabilities(EmitContext& ctx, Id main_func) {
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if (ctx.runtime_info.xfb_count == 0) {
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return;
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}
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ctx.AddCapability(spv::Capability::TransformFeedback);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::Xfb);
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}
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void SetupCapabilities(const Profile& profile, const Info& info, EmitContext& ctx) {
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if (info.uses_sampled_1d) {
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ctx.AddCapability(spv::Capability::Sampled1D);
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}
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if (info.uses_image_1d) {
|
|
ctx.AddCapability(spv::Capability::Image1D);
|
|
}
|
|
if (info.uses_sparse_residency) {
|
|
ctx.AddCapability(spv::Capability::SparseResidency);
|
|
}
|
|
if (info.uses_demote_to_helper_invocation && profile.support_demote_to_helper_invocation) {
|
|
if (profile.supported_spirv < 0x00010600) {
|
|
ctx.AddExtension("SPV_EXT_demote_to_helper_invocation");
|
|
}
|
|
ctx.AddCapability(spv::Capability::DemoteToHelperInvocation);
|
|
}
|
|
if (info.stores[IR::Attribute::ViewportIndex] && profile.support_multi_viewport) {
|
|
ctx.AddCapability(spv::Capability::MultiViewport);
|
|
}
|
|
if (info.stores[IR::Attribute::ViewportMask] && profile.support_viewport_mask) {
|
|
ctx.AddExtension("SPV_NV_viewport_array2");
|
|
ctx.AddCapability(spv::Capability::ShaderViewportMaskNV);
|
|
}
|
|
if (info.stores[IR::Attribute::Layer] || info.stores[IR::Attribute::ViewportIndex]) {
|
|
if (profile.support_viewport_index_layer_non_geometry && ctx.stage != Stage::Geometry) {
|
|
ctx.AddExtension("SPV_EXT_shader_viewport_index_layer");
|
|
ctx.AddCapability(spv::Capability::ShaderViewportIndexLayerEXT);
|
|
}
|
|
}
|
|
if (!profile.support_vertex_instance_id &&
|
|
(info.loads[IR::Attribute::InstanceId] || info.loads[IR::Attribute::VertexId])) {
|
|
ctx.AddExtension("SPV_KHR_shader_draw_parameters");
|
|
ctx.AddCapability(spv::Capability::DrawParameters);
|
|
}
|
|
if ((info.uses_subgroup_vote || info.uses_subgroup_invocation_id ||
|
|
info.uses_subgroup_shuffles) &&
|
|
profile.support_vote && profile.SupportsSubgroupStage(ctx.stage)) {
|
|
ctx.AddCapability(spv::Capability::GroupNonUniformBallot);
|
|
ctx.AddCapability(spv::Capability::GroupNonUniformShuffle);
|
|
if (!profile.warp_size_potentially_larger_than_guest) {
|
|
// vote ops are only used when not taking the long path
|
|
ctx.AddCapability(spv::Capability::GroupNonUniformVote);
|
|
}
|
|
}
|
|
if (info.uses_int64_bit_atomics && profile.support_int64_atomics) {
|
|
ctx.AddCapability(spv::Capability::Int64Atomics);
|
|
}
|
|
if (info.uses_typeless_image_reads && profile.support_typeless_image_loads) {
|
|
ctx.AddCapability(spv::Capability::StorageImageReadWithoutFormat);
|
|
}
|
|
if (info.uses_typeless_image_writes) {
|
|
ctx.AddCapability(spv::Capability::StorageImageWriteWithoutFormat);
|
|
}
|
|
if (info.uses_image_buffers) {
|
|
ctx.AddCapability(spv::Capability::ImageBuffer);
|
|
}
|
|
if (info.uses_sample_id) {
|
|
ctx.AddCapability(spv::Capability::SampleRateShading);
|
|
}
|
|
if (info.uses_derivatives) {
|
|
ctx.AddCapability(spv::Capability::DerivativeControl);
|
|
}
|
|
// TODO: Track this usage
|
|
ctx.AddCapability(spv::Capability::ImageGatherExtended);
|
|
ctx.AddCapability(spv::Capability::ImageQuery);
|
|
ctx.AddCapability(spv::Capability::SampledBuffer);
|
|
// TODO: this usage needs to be tracked properly
|
|
if (ctx.profile.support_sampled_image_array_nonuniform_indexing) {
|
|
if (ctx.profile.supported_spirv < 0x00010400)
|
|
ctx.AddExtension("SPV_EXT_descriptor_indexing");
|
|
ctx.AddCapability(spv::Capability::ShaderNonUniform);
|
|
ctx.AddCapability(spv::Capability::SampledImageArrayNonUniformIndexing);
|
|
}
|
|
}
|
|
|
|
void PatchPhiNodes(IR::Program& program, EmitContext& ctx) {
|
|
// Flatten all leading PHIs from each block into a vector
|
|
std::vector<IR::Inst*> phi_instructions;
|
|
for (IR::Block* block : program.blocks) {
|
|
for (auto it = block->begin(); it != block->end(); ++it) {
|
|
if (it->GetOpcode() != IR::Opcode::Phi)
|
|
break;
|
|
phi_instructions.push_back(&*it);
|
|
}
|
|
}
|
|
|
|
if (phi_instructions.empty()) {
|
|
return; // nothing to patch
|
|
}
|
|
|
|
// Start "before" first PHI; advance on phi_arg == 0
|
|
size_t phi_index = static_cast<size_t>(-1);
|
|
|
|
ctx.PatchDeferredPhi([&](size_t phi_arg, Id parent) -> std::pair<Id, Id> {
|
|
if (phi_arg == 0) {
|
|
++phi_index;
|
|
}
|
|
IR::Inst* phi = phi_instructions[phi_index];
|
|
return { ctx.Def(phi->Arg(phi_arg)), parent };
|
|
});
|
|
}
|
|
} // Anonymous namespace
|
|
|
|
std::vector<u32> EmitSPIRV(const Profile& profile, const RuntimeInfo& runtime_info, IR::Program& program, Bindings& bindings) {
|
|
EmitContext ctx{profile, runtime_info, program, bindings};
|
|
const Id main{DefineMain(ctx, program)};
|
|
DefineEntryPoint(program, ctx, main);
|
|
if (profile.support_float_controls) {
|
|
ctx.AddExtension("SPV_KHR_float_controls");
|
|
SetupDenormControl(profile, program, ctx, main);
|
|
SetupSignedNanCapabilities(profile, program, ctx, main);
|
|
}
|
|
SetupCapabilities(profile, program.info, ctx);
|
|
SetupTransformFeedbackCapabilities(ctx, main);
|
|
PatchPhiNodes(program, ctx);
|
|
return ctx.Assemble();
|
|
}
|
|
|
|
Id EmitPhi(EmitContext& ctx, IR::Inst* inst) {
|
|
const size_t num_args{inst->NumArgs()};
|
|
boost::container::small_vector<Id, 32> blocks;
|
|
blocks.reserve(num_args);
|
|
for (size_t index = 0; index < num_args; ++index) {
|
|
blocks.push_back(inst->PhiBlock(index)->Definition<Id>());
|
|
}
|
|
// The type of a phi instruction is stored in its flags
|
|
const Id result_type{TypeId(ctx, inst->Flags<IR::Type>())};
|
|
return ctx.DeferredOpPhi(result_type, std::span(blocks.data(), blocks.size()));
|
|
}
|
|
|
|
void EmitVoid(EmitContext&) {}
|
|
|
|
Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
|
|
const Id id{ctx.Def(value)};
|
|
if (!Sirit::ValidId(id)) {
|
|
throw NotImplementedException("Forward identity declaration");
|
|
}
|
|
return id;
|
|
}
|
|
|
|
Id EmitConditionRef(EmitContext& ctx, const IR::Value& value) {
|
|
const Id id{ctx.Def(value)};
|
|
if (!Sirit::ValidId(id)) {
|
|
throw NotImplementedException("Forward identity declaration");
|
|
}
|
|
return id;
|
|
}
|
|
|
|
void EmitReference(EmitContext&) {}
|
|
|
|
void EmitPhiMove(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetZeroFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetSignFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetCarryFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetOverflowFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetSparseFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetInBoundsFromOp(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
} // namespace Shader::Backend::SPIRV
|